Abstract: A pre-production, prototype multi-chip module adapted for preliminary performance timing and functional tests includes a plurality of chips attached to a substrate. Multiple nets are embedded within the substrate connecting the chips. A layer over the substrate encapsulates the chips. Production input/output pins on the substrate are connected to the chips. An area on the upper surface of the module is not covered by the encapsulating layer, which contains upper pads adapted for connection of a second module containing spare circuits to the substrate, wherein the upper pads are connected to the at least one net. Some of the upper pads have connections to each other near the surface of the encapsulating layer, wherein the connections are adapted to be severed for connecting a second module containing spare circuits to one or more of the chips.