Abstract: A processor includes a central processing unit (CPU) and a direct memory access (DMA) adapter circuit. The DMA adapter circuit includes a DMA controller circuit and is configured to interface with a legacy internal hardware peripheral and with a DMA-enabled internal hardware peripheral. The DMA-enabled internal hardware peripheral includes a first special function register (SFR). The legacy internal hardware peripheral includes no DMA features. The CPU is configured to execute a legacy application that accesses a setting in memory through the legacy internal hardware peripheral. Execution of the legacy application includes access by the CPU of the setting in memory. The DMA controller circuit is configured to access the setting in memory during execution of a DMA-enabled application through the DMA-enabled internal hardware peripheral.

Abstract: A processor includes a central processing unit (CPU) and a direct memory access (DMA) adapter circuit. The DMA adapter circuit includes a DMA controller circuit and is configured to interface with a legacy internal hardware peripheral and with a DMA-enabled internal hardware peripheral. The DMA-enabled internal hardware peripheral includes a first special function register (SFR). The legacy internal hardware peripheral includes no DMA features. The CPU is configured to execute a legacy application that accesses a setting in memory through the legacy internal hardware peripheral. Execution of the legacy application includes access by the CPU of the setting in memory. The DMA controller circuit is configured to access the setting in memory during execution of a DMA-enabled application through the DMA-enabled internal hardware peripheral.

Abstract: A digitally controlled ramp generator has a constant current source, a first controllable switch coupled between the constant current source and an output node, a capacitor coupled with the output node, a second controllable switch coupled with the output node, a constant current sink coupled with the second controllable switch, and a control unit. The control unit is configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch wherein the control signals can be selected from the group of a time based control signal and a voltage based control signal. A variety of other control modes may be provided.

Abstract: A BLDC motor drive system may be configured to provide a programmable PWM current waveform, e.g., a sinusoidal PWM current, to the motor. The drive system may include control electronics configured to generate a series of PWM control signals at a control signal frequency based on (a) the present motor speed data as determined by an angular timer, based on sensor-based rotor angle data, (b) a target motor speed, e.g., based on a thermal management unit, and (c) stored current waveform data defining a target current for each angular segment of the BDLC rotor, the target currents defining an non-rectangular waveform shape. The PWM control signals are used by a PWM unit to produce a non-rectangular, e.g., sinusoidal, PWM current for controlling the BDLC.

Abstract: A system may have a digital period divider generating an output signal that is proportional to an angle defined by a rotational input signal and an interval measurement unit determining an interval time of an interval defined by succeeding pulses of the input output signal. In an enhancement, the system may also have a missing pulse detector which is operable to compare a current interval with a parameter to determine whether a pulse is missing in the input signal.

Abstract: A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.

Abstract: External conditions, e.g., smoke, temperature, humidity, humidity, pressure, flow rate, etc., affects a sensor's characteristics, wherein the sensor provides a current output representative of its characteristics as affected by the external conditions. The current output of the sensor is coupled to a sample and hold capacitor for a precision time period thereby charging the sample and hold capacitor to a voltage proportional to current provided by the sensor over the precision time period. The voltage on the sample and hold capacitor is converted to a digital representation and a determination is made whether the external condition represents an alarm situation, e.g., smoke detected from a fire.

Abstract: An ion chamber provides a current representative of its characteristics as affected by external conditions, e.g., clean air or smoke. A direct current (DC) voltage is applied to the ion chamber at a first polarity and the resulting current through the ion chamber and parasitic leakage current is measured at the first polarity, then the DC voltage is applied to the ion chamber at a second polarity opposite the first polarity, and the resulting current through the ion chamber and parasitic leakage current is measured at the second polarity. Since substantially no current flows through the ion chamber at the second polarity, the common mode parasitic leakage current contribution may be removed from the total current measurement by subtracting the current measured at the second polarity from the current measured at the first polarity, resulting in just the current through the ion chamber.

Abstract: A combined power and input/output system for an electronic device includes a host system; a target system operably coupled to the host system via a combined power and I/O line; and a power boost circuit in the target system for enabling a higher voltage target device.

Abstract: In a pulse width modulation light emitting diode (LED) controller an error amplifier and output load switch are synchronously controlled to prevent service life shortening current overshoot through the LEDs and slowing discharging currents causing color temperature shifting in the light output from the LEDs. A plurality of switching arrangements for the error amplifier and the compensation network may be provided in a single integrated circuit LED dimming controller, and outputs for controlling a variety of differently configured output power switch combinations for disconnecting or shorting the LEDs, or disconnecting the output capacitor during off times of the modulated dimming control signal.

Abstract: A method for expanding a data memory for a microprocessor architecture which uses a bank select accessing scheme for accessing data memory which is divided into a plurality of memory banks. A bank select register is configured to select a memory bank and the microprocessor architecture has an instruction set with a dedicated instruction for selecting a memory bank. An opcode of the dedicated bank select instruction provides for a maximum of n bits payload thereby providing for an address value which is configured to select a maximum of 2n memory banks. The method has the steps of: using an opcode of a test instruction that provides for m bits of payload for a new bank select instruction, wherein m>n; and using an opcode of the dedicated bank select instruction for a new test instruction.

Abstract: A combined power and input/output system for an electronic device includes a host system; a target system operably coupled to the host system via a combined power and I/O line; and a power boost circuit in the target system for enabling a higher voltage target device.

Abstract: A combined power and input/output system for an electronic device includes a host system; a target system operably coupled to the host system via a combined power and I/O line; and a power boost circuit in the target system for enabling a higher voltage target device.

Abstract: An ion chamber provides a current representative of its characteristics as affected by external conditions, e.g., clean air or smoke. A direct current (DC) voltage is applied to the ion chamber at a first polarity and the resulting current through the ion chamber and parasitic leakage current is measured at the first polarity, then the DC voltage is applied to the ion chamber at a second polarity opposite the first polarity, and the resulting current through the ion chamber and parasitic leakage current is measured at the second polarity. Since substantially no current flows through the ion chamber at the second polarity, the common mode parasitic leakage current contribution may be removed from the total current measurement by subtracting the current measured at the second polarity from the current measured at the first polarity, resulting in just the current through the ion chamber.

Abstract: An ion chamber provides a current representative of its characteristics as affected by external conditions, e.g., clean air or smoke. A direct current (DC) voltage is applied to the ion chamber at a first polarity and the resulting current through the ion chamber and parasitic leakage current is measured at the first polarity, then the DC voltage is applied to the ion chamber at a second polarity opposite the first polarity, and the resulting current through the ion chamber and parasitic leakage current is measured at the second polarity. Since substantially no current flows through the ion chamber at the second polarity, the common mode parasitic leakage current contribution may be removed from the total current measurement by subtracting the current measured at the second polarity from the current measured at the first polarity, resulting in just the current through the ion chamber.

Abstract: A light emitting diode (LED) is driven with a plurality of pulses having controllable pulse widths and positions within clock time periods that provide for both LED light intensity control and digital information communications from a single output node of an integrated circuit (IC) device. The LED light intensity is determined by the duty cycle of the pulses where the human eye integrates these light pulses from the LED into continuous light intensity levels. The digital information contained in the light output from the LED is detected by a photo-detector that converts the light pulses into electric signals that are demodulated and read by a circuit debugger and/or manufacturing test station. The aforementioned operations allow continuous visual display and data transmission using only one output node of the IC device. This is especially advantageous when using low pin count IC devices.

Abstract: A smoke detection sensor ion chamber has a leakage current that is dependent upon the permittivity of the ionized gas (air) in the chamber. Smoke from typical fires is mainly composed of unburned carbon that has diffused in the surrounding air and rises with the heat of the fire. The permittivity of the carbon particles is about 10 to 15 times the permittivity of clean air. The addition of the carbon particles into the air in the ion chamber changes the permittivity thereof that is large enough to detect by measuring a change in the leakage current of the ion chamber.

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract: In a pulse width modulation light emitting diode (LED) controller an error amplifier and output load switch are synchronously controlled to prevent service life shortening current overshoot through the LEDs and slowing discharging currents causing color temperature shifting in the light output from the LEDs. A plurality of switching arrangements for the error amplifier and the compensation network may be provided in a single integrated circuit LED dimming controller, and outputs for controlling a variety of differently configured output power switch combinations for disconnecting or shorting the LEDs, or disconnecting the output capacitor during off times of the modulated dimming control signal.

Abstract: A smoke detection sensor ion chamber has a capacitance and a change in the permittivity of that capacitance dielectric (ionized air in the chamber) may be used to detect the presence of smoke therein. Smoke from typical fires is mainly composed of unburned carbon that has diffused in the surrounding air and rises with the heat of the fire. The permittivity of the carbon particles is about 10 to 15 times the permittivity of clean air. The addition of the carbon particles into the air in the ion chamber changes in the permittivity thereof that is large enough to measure by measuring a change in capacitance of the ion chamber.