Patents by Inventor Joseph K. Fauty
Joseph K. Fauty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8319323Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.Type: GrantFiled: December 20, 2004Date of Patent: November 27, 2012Assignee: Semiconductor Components Industries, LLCInventors: James P. Letterman, Jr., Joseph K. Fauty, Jay A. Yoder, William F. Burghout
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Patent number: 8253239Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.Type: GrantFiled: November 30, 2010Date of Patent: August 28, 2012Assignee: Semiconductor Components Industries, LLCInventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Publication number: 20110068451Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Patent number: 7901990Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.Type: GrantFiled: September 3, 2009Date of Patent: March 8, 2011Assignee: Semiconductor Components Industries, LLCInventors: James P. Letterman, Jr., Kent L. Kime, Joseph K. Fauty
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Patent number: 7875964Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.Type: GrantFiled: February 7, 2007Date of Patent: January 25, 2011Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Patent number: 7820528Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: GrantFiled: August 4, 2009Date of Patent: October 26, 2010Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Patent number: 7656048Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.Type: GrantFiled: April 22, 2008Date of Patent: February 2, 2010Assignee: Semiconductor Components Industries, LLCInventors: Joseph K. Fauty, James P. Letterman, Jr., Denise Thienpont
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Publication number: 20100019367Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.Type: ApplicationFiled: September 3, 2009Publication date: January 28, 2010Inventors: James P. Letterman, JR., Kent L. Kime, Joseph K. Fauty
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Publication number: 20100000772Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.Type: ApplicationFiled: December 20, 2004Publication date: January 7, 2010Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.Inventors: James P. Letterman, JR., Joseph K. Fauty, Jay A. Yoder, William F. Burghout
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Publication number: 20090298232Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: ApplicationFiled: August 4, 2009Publication date: December 3, 2009Inventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Patent number: 7602054Abstract: In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.Type: GrantFiled: October 5, 2005Date of Patent: October 13, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: James P. Letterman, Jr., Kent L. Kime, Joseph K. Fauty
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Patent number: 7598123Abstract: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.Type: GrantFiled: March 2, 2007Date of Patent: October 6, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Jay A. Yoder, Joseph K. Fauty, James P. Letterman
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Patent number: 7588999Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: GrantFiled: October 28, 2005Date of Patent: September 15, 2009Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Patent number: 7508060Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.Type: GrantFiled: September 24, 2007Date of Patent: March 24, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Patent number: 7498195Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.Type: GrantFiled: February 12, 2007Date of Patent: March 3, 2009Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Patent number: 7439100Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.Type: GrantFiled: August 18, 2005Date of Patent: October 21, 2008Assignee: Semiconductor Components Industries, L.L.C.Inventors: Joseph K. Fauty, James P. Letterman, Jr., Denise Thienpont
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Publication number: 20080217765Abstract: A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.Type: ApplicationFiled: March 2, 2007Publication date: September 11, 2008Inventors: Jay A. Yoder, Joseph K. Fauty, James P. Letterman
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Publication number: 20080197459Abstract: In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.Type: ApplicationFiled: April 22, 2008Publication date: August 21, 2008Inventors: Joseph K. Fauty, James P. Letterman, Denise Thienpont
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Patent number: 7298034Abstract: In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.Type: GrantFiled: June 28, 2004Date of Patent: November 20, 2007Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
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Patent number: 7202106Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.Type: GrantFiled: June 28, 2004Date of Patent: April 10, 2007Assignee: Semiconductor Components Industries, L.L.C.Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder