Abstract: Field emission devices may include emitter wells formed in a body of dielectric material. A gate conductor may be provided along the upper surface of the dielectric material. A gate hole may be provided in the gate conductor directly above each of the emitter wells. A method for forming the gate holes and emitter wells is disclosed. The method includes the steps of providing a first gate conductor layer on a dielectric layer. A pattern of second gate conductor material may be formed over the first gate conductor layer, said pattern defining gate holes in the second gate conductor material. The gate holes may then be completed and emitter wells formed by etching through the first gate conductor layer and into the dielectric layer using an etch that selectively etches the first gate conductor layer and the dielectric layer, and does not etch substantially the second gate conductor material.

Abstract: A field emitter device includes a column conductor, an insulator, and a resistor structure for advantageously limiting current in a field emitter array. A wide column conductor is deposited on an insulating substrate. An insulator is laid over the column conductor. A high resistance layer is placed on the insulator and is physically isolated from the column conductor. The high resistance material may be chromium oxide or 10%-50% wt % Cr+SiO. A group of microtip electron emitters is placed over the high resistance layer. A low resistance strap interconnects the column conductor with the high resistance layer to connect in an electrical series circuit the column conductor, the high resistance layer, and the group of electron emitters. One or more layers of insulator and a gate electrode, all with cavities for the electron emitters, are laid over the high resistance material. One layer of insulator is selected from a group of materials including SiC, SiO, and Si.sub.3 N.sub.4.