Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.