Abstract: Techniques for transmitting a packet from a source switch module to a destination switch module. Embodiments receive, at a first port of a first switch module, a packet that includes (i) path information specifying a route to the destination switch module and (ii) a set of load/store operations to be executed by the destination switch module. An indication of the first port is inserted into a return path information portion of the received packet. Upon determining that the first switch module is not the destination switch module, embodiments transmit the packet to a second switch module using a second port, the second port specified in the path information of the received packet, wherein the destination switch module is configured, upon receiving the packet, to copy the set of load/store operations into an execution buffer to be automatically executed.

Abstract: Receive a request to write a unit of data, having a first half of bits and a second half of bits, to an index of a ternary content addressable memory (TCAM). Generate a first error-correcting code (ECC) codeword for first bits of the first half of bits of the unit of data and first bits of the second half of bits of the unit of data. Generate a second error-correcting code (ECC) codeword for second bits of the first half of bits of the unit of data and second bits of the second half of bits of the unit of data. Store the first half of bits of the unit of data in the first row of the index. Store the second half of bits of the unit of data in the second row of the index.

Abstract: Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed.

Abstract: A system and method for efficient transfer of data from a controlling bridge to a register of a distributed bridge element. A Load Store over Ethernet (LSoE) frame processing engine (FPE) is equipped with a repeat and a repeat with strobe function that, when coupled with an auto-increment function of an indirect register facility, allows a distributed virtual bridge to move data payload more efficiently which decreases the data loading on the computers data paths used for other data transfers.

Abstract: A system and method for efficient transfer of data in a data from a controlling bridge to a register of a distributed bridge element. A Load Store over Ethernet (LSoE) frame processing engine (FPE) is equipped with a repeat and a repeat with strobe function that, when coupled with an auto-increment function of an indirect register facility, allows a distributed virtual bridge to move data payload more efficiently which decreases the data loading on the computers data paths used for other data transfers.

Abstract: Techniques for transmitting a packet from a source switch module to a destination switch module. Embodiments retrieve path information specifying a route to the destination switch module. A packet is created that includes (i) at least a portion of the path information and (ii) a set of load/store operations to be executed by the destination switch module. Embodiments then transmit the packet to a first switch module using a first port, the first port specified in the retrieved path information. The first switch module is configured to transmit the packet based on the at least a portion of the path information in the packet, and the destination switch module is configured, upon receiving the packet, to copy the set of load/store operations into an execution buffer to be automatically executed.

Abstract: Techniques for transmitting a packet from a source switch module to a destination switch module. Embodiments receive, at a first port of a first switch module, a packet that includes (i) path information specifying a route to the destination switch module and (ii) a set of load/store operations to be executed by the destination switch module. An indication of the first port is inserted into a return path information portion of the received packet. Upon determining that the first switch module is not the destination switch module, embodiments transmit the packet to a second switch module using a second port, the second port specified in the path information of the received packet, wherein the destination switch module is configured, upon receiving the packet, to copy the set of load/store operations into an execution buffer to be automatically executed.

Abstract: Techniques for transmitting a packet from a source switch module to a destination switch module. Embodiments receive, at a first port of a first switch module, a packet that includes (i) path information specifying a route to the destination switch module, (ii) a set of load/store operations to be executed by the destination switch module and (iii) return path information specifying a route from the destination switch module to the source switch module. Upon determining that the first switch module is the destination switch module, the set of load/store operations are copied from the received packet into an execution buffer for automatic execution. Once the set of load/store operations are executed, embodiments transmit the packet to a second switch module using the first port on which the packet was received.

Abstract: Techniques are described for transmitting a packet from a source switch module to a destination switch module. Embodiments include determining, at the destination switch module, a path from the source switch module to the destination switch module. Path information specifying the determined path from the source switch module to the destination switch module is transmitted from the destination switch module to the source switch module. Additionally, embodiments include receiving, at the destination switch module, from the source switch module, a packet that includes (i) at least a portion of the path information and (ii) payload data to be processed at the destination switch module, wherein the packet was routed using the at least a portion of the path information. The payload data within the received packet is processing by the destination switch module.

Abstract: Techniques are described for transmitting a packet from a source switch module to a destination switch module. Embodiments receive, at the source switch module, from the destination switch module, path information specifying a path from the source switch module to the destination switch module. Upon detecting an occurrence of a predefined event, a packet is generated that includes (i) the received path information and (ii) payload data to be processed at the destination switch module. Embodiments determine an Ethernet port of the source switch module on which to transmit the packet, based on the received path information. The packet is transmitted to a second switch module using the determined Ethernet port.

Abstract: Techniques are described for transmitting a packet from a source switch module to a destination switch module. Embodiments include receiving, at a first switch module, a packet that includes (i) an ordered listing of Ethernet link identifiers, specifying a path to the destination switch module and (ii) payload data to be processed at the destination switch module. Embodiments determine that the first switch module is not a destination of the packet, based on the ordered listing of Ethernet link identifiers. Additionally, an Ethernet port of the first switch module on which to transmit the packet is determined based on the ordered listing of Ethernet link identifiers. Embodiments then transmit the packet to a second switch module using the determined Ethernet port of the first switch module.

Abstract: Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed.

Abstract: Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed.

Abstract: Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed.

Abstract: Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port.

Abstract: Systems and methods to respond to error detection are provided. A particular method may include issuing a first command to a first redrive device and a second command to a second redrive device. The method may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method may further include storing at a first buffer first data that is received from the first redrive device in response to the first command. The method may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also may include merging the second data with the first data.

Abstract: Systems and methods to manage memory refreshes at a memory controller are disclosed. A method includes determining, at a memory controller device, that a number of transmission errors between a memory controller port and a memory redrive device exceeds an error threshold. The method may include initiating a first link retraining process between the memory controller port and the memory redrive device. The method may further include placing one or more dynamic random access memory modules associated with the memory redrive device in a self-refresh mode. The method may also include removing the one or more dynamic random access memory modules from the self-refresh mode after the link retraining process has completed. The method may further include enabling overlapping refreshes of the one or more dynamic random access memory modules.

Abstract: A compressed replay buffer in a first electronic unit of an electronic system holds commands in a table. As commands are transmitted from the first electronic unit to a second electronic unit, the command, along with associated data, command type, and the like are stored in a row in the table. No rows in the table contain “dead cycles” to indicate that no command was sent on a particular cycle on a bus over which the commands were transmitted. The second electronic unit may request that the first electronic unit replay some number of commands. In response, the first electronic unit uses commands in the compressed replay buffer, along with required timings stored on the first electronic unit, to replay the number of commands requested.

Abstract: In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending a first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.

Abstract: Systems and methods to respond to schedule commands at a memory controller are disclosed. A transmission error between a first memory controller port and a first redrive device may be detected. A first corrective action may be initiated at the first memory controller port in response to the detection of the transmission error. A particular method may include determining that a second memory controller port initiated a second corrective action. Incoming read commands may be distributed based on a comparison of the first corrective action and the second corrective action.