Patents by Inventor Joseph Kotylo

Joseph Kotylo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7087441
    Abstract: A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different metal or metal alloy composition. In each embodiment, a single commoning layer (e.g., copper) is used, being partially removed following the first deposition. The solder is deposited using an electroplating process (electroless or electrolytic) and the commoning bar in both depositing steps. An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: August 8, 2006
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John J. Konrad, Joseph A. Kotylo, Jose A. Rios
  • Publication number: 20060099727
    Abstract: A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different metal or metal alloy composition. In each embodiment, a single commoning layer (e.g., copper) is used, being partially removed following the first deposition. The solder is deposited using an electroplating process (electroless or electrolytic) and the commoning bar in both depositing steps. An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described.
    Type: Application
    Filed: October 21, 2004
    Publication date: May 11, 2006
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: John Konrad, Joseph Kotylo, Jose Rios
  • Patent number: 6931722
    Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corporation
    Inventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
  • Publication number: 20030177635
    Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 25, 2003
    Inventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A. Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
  • Patent number: 6586683
    Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A. Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
  • Publication number: 20020157861
    Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.
    Type: Application
    Filed: April 27, 2001
    Publication date: October 31, 2002
    Applicant: International Business Machines Corporation
    Inventors: Edward L. Arrington, Anilkumar C. Bhatt, Edmond O. Fey, Kevin T. Knadle, John J. Konrad, Joseph A. Kotylo, Jeffrey McKeveny, Jose A. Rios, Amit K. Sarkhel, Andrew M. Seman, Timothy L. Wells
  • Patent number: 6009620
    Abstract: A method of making a circuitized substrate wherein fill material is forced into the substrate's holes to thus provide additional support for conductive circuitry or the like thereon, thus increasing the final product's circuit density. The fill is provided in a substantially uncured state, following which partial cure occurs. Thereafter, the fill is substantially fully cured and the aforementioned circuit elements may then be provided directly thereon. Alternatively, a dual fill process is used with both quantities of uncured fill being disposed in each hole and then cured by a singular UV exposure step.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: January 4, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ashwinkumar C. Bhatt, Joseph A. Kotylo, Kenneth S. Lyjak, Amarjit S. Rai, John A. Welsh
  • Patent number: 5268260
    Abstract: Simple, environmentally friendly developers and strippers are disclosed for free radical-initiated, addition polymerizable resists, cationically cured resists and solder masks and Vacrel photoresists. In all cases both the developers and the strippers include gamma butyrolactone, propylene carbonate and benzyl alcohol, optionally also including a minor amount of methanol, ethanol, isopropyl alcohol, propylene glycol monomethylacetate, ethylene glycol monomethyl ether, formamide, nitromethane, propylene oxide, or methyl ethyl ketone, acetone and water.
    Type: Grant
    Filed: October 22, 1991
    Date of Patent: December 7, 1993
    Assignee: International Business Machines Corporation
    Inventors: Nageshwer R. Bantu, Anilkumar C. Bhatt, Ashwinkumar C. Bhatt, Joseph A. Kotylo, Gerald W. Jones, Robert J. Owen, Kostas Papathomas, Anaya K. Vardya