Abstract: A method for forming trenches in a device layer disposed on a silicon semiconductor substrate comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and, during the removal of semiconductor material, exposing the sidewalls to a passivating agent in increasing amounts, thereby passivating the sidewalls while reducing lateral etching of semiconductor material from them.

Abstract: A process for constructing a trench MOS-gated device includes: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.

Abstract: A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench. The drain zone is substantially insulated from the extended zone by the dielectric-filled bottom segment of the trench.

Abstract: Trenches are made in an integrated circuit by a process that incrementally increases the amount of oxygen during a trench etch. The trench may be an isolation trench or a gate trench for a QVDMOS device.

Abstract: A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench.

Abstract: A method for forming trenches in a device layer disposed on a silicon semiconductor substrate comprises: covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and, during the removal of semiconductor material, exposing the sidewalls to a passivating agent in increasing amounts, thereby passivating the sidewalls while reducing lateral etching of semiconductor material from them.