Patents by Inventor Joseph L. Ganley
Joseph L. Ganley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7398498Abstract: Some embodiments of the invention provide a method that pre-computes routes for groups of related net configurations. These routes are used by a router that uses a set of partitioning lines to partition a region of a design layout into a plurality of sub-regions. The method identifies groups of related sub-region configurations. For each group, the method stores a base set of routes. For each configuration in each group, the method also stores an indicia that specifies how to obtain a related set of routes for the particular configuration from the base set of routes stored for the configuration's group.Type: GrantFiled: January 4, 2002Date of Patent: July 8, 2008Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 7143382Abstract: Some embodiments of the invention provide a method of pre-computing routes for nets a region of a design layout. These routes are used by a router that uses a set of partitioning lines to partition the region into a plurality of sub-regions. For each particular set of potential sub-regions, the method initially identifies a set of routes that traverse the particular set of potential sub-regions. For each particular route identified for each particular set of sub-regions, the method then determines whether the particular route is stored in a storage structure. If not, the method stores the particular route in the storage structure.Type: GrantFiled: January 4, 2002Date of Patent: November 28, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 7139994Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit (“IC”) layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a set of routes that traverse the particular set of potential sub-regions, where at least one of the identified routes has at least one diagonal edge. The method then stores the identified routes.Type: GrantFiled: January 7, 2002Date of Patent: November 21, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley, Heng-Yi Chao
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Patent number: 7100137Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.Type: GrantFiled: December 19, 2000Date of Patent: August 29, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 7089523Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.Type: GrantFiled: December 13, 2000Date of Patent: August 8, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 7080336Abstract: For a placer that partitions a region of a circuit layout into a plurality of sub-regions, some embodiments provide a method of computing placement costs. For a set of sub-regions, the method identifies a connection graph that connects the set of sub-regions. The connection graph has at least one edge that is at least partially diagonal. The method then identifies a placement cost from an attribute of the connection graph.Type: GrantFiled: February 20, 2002Date of Patent: July 18, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 7055120Abstract: Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the delay cost of a placement configuration by accounting for the potential use of diagonal wiring in the layout. Some of these embodiments derive the delay cost from an estimate of the wirelength needed to route the nets in the region.Type: GrantFiled: January 13, 2002Date of Patent: May 30, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 7024650Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.Type: GrantFiled: December 6, 2000Date of Patent: April 4, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6988256Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.Type: GrantFiled: December 15, 2000Date of Patent: January 17, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6910198Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins of circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.Type: GrantFiled: December 15, 2000Date of Patent: June 21, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6907593Abstract: Some embodiments provide a method of pre-computing attributes of routes for nets in a region of a design layout. The pre-computed attributes are used by an electronic design automation application that partitions a design-layout region into a plurality of sub-region.Type: GrantFiled: January 13, 2002Date of Patent: June 14, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6904580Abstract: Some embodiments of the invention provide a method that pre-computes costs of placing circuit modules in regions of circuit layouts. The method defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a placement operation. For each set of potential sub-regions, the method identifies a connection graph that traverses the set of potential sub-regions. Some of the connection graphs have edges that are at least partially diagonal. The method then identifies an attribute of each identified connection graph. For each set of potential sub-regions, the method then stores the identified attribute of the connection graph that is identified for the set.Type: GrantFiled: February 20, 2002Date of Patent: June 7, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6848091Abstract: Some embodiments of the invention are placers that use lines that are not orthogonal with each other to calculate the costs of potential placement configurations. Some of these embodiments use non-orthogonal lines to measure congestion costs of potential placement configurations. For instance, some embodiments use non-orthogonal lines as cut lines that divide the IC layout into regions. These embodiments then generate congestion-cost estimates by measuring the number of nets cut by the cut lines.Type: GrantFiled: December 23, 2002Date of Patent: January 25, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6826737Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in a IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.Type: GrantFiled: December 6, 2000Date of Patent: November 30, 2004Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6802049Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.Type: GrantFiled: December 15, 2000Date of Patent: October 5, 2004Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6795958Abstract: Some embodiments of the invention provide a method that identifies a set of routes for a net that has a set of pins in a region of a design layout. The method initially partitions the region into a number of sub-regions. It then identifies a first set of sub-regions that contains the net's pins. Based on the first set of sub-regions, the method identifies a first route that traverses a second set of sub-regions. The first and second sets of sub-regions have a particular relationship. Based on this particular relationship, the method identifies a second route from the first route, where the second route traverses the first set of sub-regions.Type: GrantFiled: January 4, 2002Date of Patent: September 21, 2004Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Publication number: 20040123260Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.Type: ApplicationFiled: December 15, 2000Publication date: June 24, 2004Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6687893Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit (“IC”) layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a first set of routes based on a first wiring model and a second set of routes based on a second wiring model. Each identified set of routes traverses the particular set of potential sub-regions. The method then stores the identified routes.Type: GrantFiled: January 7, 2002Date of Patent: February 3, 2004Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6678872Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.Type: GrantFiled: December 13, 2000Date of Patent: January 13, 2004Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley
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Patent number: 6671864Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.Type: GrantFiled: December 13, 2000Date of Patent: December 30, 2003Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley