Abstract: A system and method for recording and addressing out of control (OOC) events in a semiconductor processing line. The method includes steps of (a) opening OOC entries in an OOC database, and (b) working the OOC entries. Opening an OOC entry is performed in response to one or more OOC events in wafer lots being processed in the semiconductor processing line. A lot record addresses an isolated occurrence pertaining to one wafer lot. An issue record addresses a trend of repeated defects or failures. Opening an OOC entry in the OOC database preferably includes assigning and recording an “owner” responsible for addressing the OOC entry. Working the OOC entries includes opening activity records for the OOC entries, receiving user input on corrective measures, and recording the measures in the activity records. The method preferably also includes steps of (c) closing OOC entries after working the OOC entries, and (d) reassigning OOC entries if ownership is transferred for the entries.

Abstract: Methods of removing resist residues from semiconductor workpiece surfaces are provided. In one aspect, a method of removing resist from a surface of a workpiece is provided that includes the steps of exposing the workpiece to a plasma and rinsing the workpiece with CO2 and water in a processing chamber to dissolve the resist. Reliance on post plasma strip solvent rinses for resist removal is eliminated. The combination of CO2 with post-plasma strip water rinse increases the solubility and thus the removal rate of resist residues.

Abstract: In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500 .ANG.. By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e.g., low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1.12 eV, with a junction dopant region shallower than 1200 .ANG. and a monotonically decreasing junction dopant profile.

Abstract: In order to reduce parasitic capacitive cross-coupling in an integrated circuit, metallization lines in an array--for example, an array of word lines, of bit lines, or of bus interconnects--are geometrically arranged in a systematically progressive laterally (sidewise) marching sequence, whereby the identity of the lines located on either side of a given line keeps changing.

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks.

Abstract: A trench version of a high-capacitance (Hi-C) capacitor for a dynamic random-access-memory (DRAM) cell is made utilizing a modified version of the doping technique described in U.S. Pat. No. 4,471,524 and 4,472,212. A shallow highly doped trench region is thereby formed. At the same time, selected lateral surface portions of the structure are also thereby highly doped. These surface portions permit a direct electrical connection to be easily made between the capacitor and a subsequently formed adjacent access transistor.

Abstract: It is known to utilize dielectric-filled trenches in a CMOS integrated-circuit device to achieve electrical isolation between adjacent n-channel and p-channel regions. In that way, latchup-free operation of the device is ensured. But inversion effects along the walls of the trenches can cause high leakage currents, undesirably high parasitic capacitances and even shorting together of source/drain regions. In accordance with the invention, a nonlithographic technique including selective anodic oxidation is employed to selectively mask the sidewalls of the trenches. Each sidewall can then be independently doped thereby effectively eliminating the possibility of inversion occurring therealong.