Patents by Inventor Joseph Leo Zielke, Jr.

Joseph Leo Zielke, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, method, and computer program product for mixed signal verification
    Patent number: 11334704
    Abstract: The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function (“SV-UDR”) associated with the electronic circuit design.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 17, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Nan Zhang, Chandrashekar L. Chetput, Aaron Mitchell Spratt, Joseph Leo Zielke, Jr., Rajat Kanti Mitra