Abstract: The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer.

Abstract: An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness.

Abstract: Chemical mechanical planarization or spin etch planarization of surfaces of copper, tantalum and tantalum nitride is accomplished by means of the chemical formulations of the present invention. The chemical formulations may optionally include abrasive particles and which may be chemically reactive or inert. Contact or non-contact CMP may be performed with the present chemical formulations. Substantially 1:1 removal rate selectivity for Cu and Ta/TaN is achieved.

Abstract: The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer.

Abstract: An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness.

Abstract: The present invention describes methods and chemical compositions for the spin etch planarization of surfaces, particularly copper and tantalum. An etching solution is brought into contact with the upper face of a spinning wafer through a nozzle, preferably an oscillating nozzle. The etching solution has a composition that oxidizes the spinning surface, forming a passivation layer thereon. The etching solution further contains reactants for removing the passivation layer exposing the underlying surface to further reaction, leading to the desired etching of the surface. The characteristics of the etching solution are adjusted such that reactant diffusion to lower regions of the surface limits the rate of etching. Faster reaction occurs at higher regions of the surface lying in more rapidly moving etching solution resulting in the desired planarization.

Abstract: An electronic device comprises a substrate with a trench having a lower portion and a top portion. The lower portion of the trench is filled with a cured spin-on compound, while the top portion is filled with a chemical vapor-deposited compound. Preferably, the chemical vapor-deposited compound has a surface that is substantially coplanar with the surface of the substrate. Particularly preferred methods of fabricating such devices include a step in which a trench is formed in the substrate, and in which a first compound is deposited in the trench by spin-on deposition. The first compound is partially removed from the trench to a level below the surface of the substrate, and in a further step, a second compound is deposited onto the upper surface of the first compound by chemical vapor deposition.

Abstract: An electronic component contemplated comprises a) a substrate layer, b) a dielectric layer coupled to the substrate layer, c) a barrier layer coupled to the dielectric layer, d) a conductive layer coupled to the barrier layer, and e) a protective layer coupled to the conductive layer. The electronic component contemplated herein can be produced by a) providing a substrate; b) coupling a dielectric layer to the substrate; c) coupling a barrier layer to the dielectric layer; d) coupling a conductive layer to the barrier layer; and e) coupling a protective layer to the conductive layer. The protective layer may then be cured to a desirable hardness.

Abstract: The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer.