Abstract: Techniques for compiling firewall rules into byte code or assembly code that can be loaded into cache memory of a processor and executed to evaluate received data packets. Rather than representing firewall rules in mid- or high-level languages stored in main memory, the techniques described herein include compiling the firewall rules into bytecode or assembly code, and distributing the code to the data plane. A packet-processing device may load the code representing the firewall rules into instruction cache of the processor. Further, the packet-processing device receives a data packet and extracts packet context data indicating attributes of the packet, and load the packet context data into a data cache of the processor. The processor can then execute the byte code or assembly code representing the firewall rules to evaluate the packet context data without having to access main memory to determine whether allow or block the data packet.

Abstract: According to some embodiments, a method includes placing a device under test (DUT) in a test chamber and applying a pulse-modulated RF wireless test signal to the DUT in the test chamber. The method further includes detecting an acoustic output of the DUT. In addition or as an alternative to applying the pulse-modulated test signal, the test signal strength may be at a level of 30 V/m or 90 V/m. If the DUT is a telephone, it may be coupled via a voice signal path to another telephone, and an output of the other telephone may also be detected.

Abstract: According to some embodiments, a method includes placing a device under test (DUT) in a test chamber and applying a pulse-modulated RF wireless test signal to the DUT in the test chamber. The method further includes detecting an acoustic output of the DUT. In addition or as an alternative to applying the pulse-modulated test signal, the test signal strength may be at a level of 30 V/m or 90 V/m. If the DUT is a telephone, it may be coupled via a voice signal path to another telephone, and an output of the other telephone may also be detected.

Abstract: The graphics display system comprises a data bus for transferring a set of application pixels, wherein a set consists of W number of blocks of data, and wherein each application pixel is M number of blocks. The graphics display system further comprises an address bus for transferring memory addresses, a graphics controller for outputting pixel data on the data bus at a rate of one set per memory clock cycle and for outputting one or more column addresses on the address bus for each set, and a graphics memory configured for a memory field size of N number of blocks such that an application pixel being stored is allocated N blocks. A set of application pixels is transferred over the data bus to the graphics memory, and, one or more column addresses are transferred over the address bus during the a memory clock cycle over the address bus. In addition, a row address is transferred to the graphics memory.