Patents by Inventor Joseph M. Harvilchuck
Joseph M. Harvilchuck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5565235Abstract: A process for simultaneously selectively depositing a high purity nickel containing alloy (i.e. a nickel-boron alloy having a nickel content in excess of 99.5 percent) over a preformed metallurgy pattern (including the individual, electrically isolated contact pads and the seal band area thereon) on the top-side dielectric surface of a multi-layer ceramic module. The metallurgy pattern on such top-side surface of such module is appropriately catalyzed and then immersed in a bath which is essentially lead-free and which includes a source of nickel ions, a borane reducing agent, and an effective amount of an organic divalent sulfur compound, preferably thiodiglycollic acid.Type: GrantFiled: March 30, 1995Date of Patent: October 15, 1996Inventors: Donald W. Baudrand, Rebecca P. Fleming, John J. Gniewek, Joseph M. Harvilchuck, Arnold F. Schmeckenbecher
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Patent number: 5543584Abstract: The present invention relates generally to a new method of repairing electrical lines, and more particularly to repairing electrical lines having an opening at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the opening with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.Type: GrantFiled: February 28, 1992Date of Patent: August 6, 1996Assignee: International Business Machines CorporationInventors: Edward F. Handford, Joseph M. Harvilchuck, Mario J. Interrante, Raymond A. Jackson, Raj N. Master, Sudipta K. Ray, William E. Sablinski, Thomas A. Wassick
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Patent number: 5403650Abstract: A process for simultaneously selectively depositing a high purity nickel containing alloy (i.e. a nickel-boron alloy having a nickel content in excess of 99.5 percent) over a preformed metallurgy pattern (including the individual, electrically isolated contact pads and the seal band area thereon) on the top-side dielectric surface of a multi-layer ceramic module. The metallurgy pattern on such top-side surface of such module is appropriately catalyzed and then immersed in a bath which is essentially lead-free and which includes a source of nickel ions, a borane reducing agent, and an effective amount of an organic divalent sulfur compound, preferably thiodiglycollic acid.Type: GrantFiled: August 18, 1993Date of Patent: April 4, 1995Inventors: Donald W. Baudrand, Rebecca P. Fleming, John J. Gniewek, Joseph M. Harvilchuck, Arnold F. Schmeckenbecher
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Patent number: 5153408Abstract: The present invention relates generally to a new method of repairing electrical lines, and more praticularly to repairing electrical lines having an open at the module level with devices in place. Various methods and processes are used to repair this open or defective portion in an electrical conductor line. It could be repaired by securing a jumper wire or nugget across the open or the repair could be made by a deposition process, which includes but is not limited to filling the open with a solder type material or inserting a solder coated electrical wire and heating the solder and allowing the solder to melt and repair the open. One of the attributes of this invention is the ability to repair on a substrate or module on which active components such as chips, and passive components such as pins, capacitors, etc. have been attached. The invention also allows repair of fine line patterns which are normally not repairable by conventional techniques.Type: GrantFiled: October 31, 1990Date of Patent: October 6, 1992Assignee: International Business Machines CorporationInventors: Edward F. Handford, Joseph M. Harvilchuck, Mario J. Interrante, Raymond A. Jackson, Raj N. Master, Sudipta K. Ray, William E. Sablinski, Thomas A. Wassick
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Patent number: 5130067Abstract: A method for co-sintering ceramic/metal multi-layered ceramic substrates wherein X-Y shrinkage is controlled and X-Y distortion and Z-direction chamber are substantially eliminated. Binder-burnoff is substantially not aggravated during this process as well. The process is accomplished by applying selective forces to the surfaces of the ceramic substrates to control lateral movement while allowing Z direction shrinkage movement. Frictional force means, pneumatic forced means and weights are among the means used to supply forces. Cerium oxide is used in certain embodiments to enhance binder-burnoff.Type: GrantFiled: May 2, 1986Date of Patent: July 14, 1992Assignee: International Business Machines CorporationInventors: Philip L. Flaitz, Arlyne M. Flanagan, Joseph M. Harvilchuck, Lester W. Herron, John U. Knickerbocker, Robert W. Nufer, Charles H. Perry, Srinivasa N. Reddy, Steven P. Young
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Patent number: 5052481Abstract: The present invention dissipates the heat generated by high powered VLSI chips to a heat sink in a very efficient manner, providing a thermal resistance heretofore not possible in heat conduction module cold plate type systems. A finned internal thermal device having a flat bottom contacts the chips, while corresponding fins in a finned cooling hat mounted to a cold plate form gaps into which the fins of the finned internal thermal devices are slidably mounted. A preferred double cantilever spring between the finned internal thermal devices and fins of the finned cooling hat and a compliant thermally conductive interface such as synthetic oil between the chips and flat base of the finned internal devices provide efficient, non-rigid interfaces throughout the system, while assuring good thermal contact between the system components.Type: GrantFiled: May 26, 1988Date of Patent: October 1, 1991Assignee: International Business Machines CorporationInventors: Joseph L. Horvath, Robert G. Biskeborn, Joseph M. Harvilchuck
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Patent number: 4962294Abstract: A method for causing an open circuit in an electrical conductor is provided, including the steps of: conducting a direct current through the conductor; and applying heat at a selected location on the conductor whereat it is desired to cause the open circuit of the conductor.Type: GrantFiled: March 14, 1989Date of Patent: October 9, 1990Assignee: International Business Machines CorporationInventors: Keith F. Beckham, David C. Challener, Arunava Gupta, Joseph M. Harvilchuck, James M. Leas, James R. Lloyd, David C. Long, Horatio Quinones, Krishna Seshan, Morris Shatzkes
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Patent number: 4634638Abstract: Brazing of elements to electronic chip carrying substrates requires brazing materials strong at high temperatures used to remove and replace chips. Flanges and pins are brazed with Au:Sn brazing alloys modified during brazing by addition of copper to the brazing material to promote formation of the higher melting point .beta. phase of the alloy and a Group VIII metal to draw Sn out of the melt by gettering, also to promote formation of the .beta. phase of the alloy and to thicken the braze material. A copper preform is plated with Ni and juxtaposed with surfaces to be brazed and the brazing material to add Ni and copper to the melt.Type: GrantFiled: December 17, 1981Date of Patent: January 6, 1987Assignee: International Business Machines CorporationInventors: Norman G. Ainslie, Joseph M. Harvilchuck, Mario J. Interrante, William J. King, Jr., Paul H. Palmateer, John F. Sullivan
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Patent number: 4601424Abstract: A method for fabricating metallurgical contacts is disclosed for making thermocompression bonds to a metallized ceramic substrate on which semiconductor chips are to be mounted and electrically contacted. The method comprises placing a nickel layer on the metallized portion of the substrate and then covering the nickel with an immersion layer of gold. The gold immersion layer is selectively removed from locations where thermocompression-bonded contacts are desired. Removal is accomplished by applying a chemical stripper. Heavy gold is electroplated on said locations and the assemblage is heat treated prior to placement of the thermocompression-bonded contacts.Type: GrantFiled: May 17, 1985Date of Patent: July 22, 1986Assignee: International Business Machines CorporationInventors: Avinash S. Adwalpalker, Joseph M. Harvilchuck, Joseph R. Ranalli, David W. Rich
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Patent number: 3994793Abstract: A process for etching aluminum wherein a masked layer of aluminum, supported on a substrate, is exposed to a plasma formed by imposing an RF voltage across at least two spaced electrodes in an ambient including a gas selected from the group consisting of CCl.sub.4, Cl.sub.2, Br.sub.2, HCl. The resultant conditions provide a reactive environment where the aluminum is bombarded with chlorine or bromine ions. The aluminum reacts with chlorine or bromine ions to form an aluminum chloride or bromide compound, which is volatile at the temperature of the sputtered substrate.Type: GrantFiled: May 22, 1975Date of Patent: November 30, 1976Assignee: International Business Machines CorporationInventors: Joseph M. Harvilchuck, Joseph S. Logan, William C. Metzger, Paul M. Schaible