Patents by Inventor Joseph M. HENSLEY

Joseph M. HENSLEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Differential amplifiers with improved slew performance
    Patent number: 9899965
    Abstract: Disclosed herein are differential amplifiers for improved slew performance. In some embodiments, a differential amplifier may receive positive and negative input signals at first and second transistor branches, respectively; provide a dynamic bias current to the first and second transistor branches, responsive to the positive and negative input signals; and provide positive and negative output signals at the second and first transistor branches, respectively.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 20, 2018
    Assignee: ANALOG DEVICES, INC.
    Inventors: Michael R. Elliott, Joseph M. Hensley
  • DIFFERENTIAL AMPLIFIERS WITH IMPROVED SLEW PERFORMANCE
    Publication number: 20170093349
    Abstract: Disclosed herein are differential amplifiers for improved slew performance. In some embodiments, a differential amplifier may receive positive and negative input signals at first and second transistor branches, respectively; provide a dynamic bias current to the first and second transistor branches, responsive to the positive and negative input signals; and provide positive and negative output signals at the second and first transistor branches, respectively.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Applicant: ANALOG DEVICES, INC.
    Inventors: Michael R. Elliott, JOSEPH M. HENSLEY
  • CMOS transistor linearization method
    Patent number: 8810283
    Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: August 19, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Joseph M. Hensley, Franklin M. Murden
  • CMOS TRANSISTOR LINEARIZATION METHOD
    Publication number: 20130314128
    Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 28, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventors: Joseph M. HENSLEY, Franklin M. MURDEN