Patents by Inventor Joseph M. Jeddeloh
Joseph M. Jeddeloh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11868267Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: GrantFiled: March 30, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Patent number: 11556465Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.Type: GrantFiled: February 12, 2021Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
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Publication number: 20220222181Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: ApplicationFiled: March 30, 2022Publication date: July 14, 2022Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Patent number: 11301391Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: GrantFiled: August 31, 2020Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Patent number: 11042441Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.Type: GrantFiled: July 1, 2019Date of Patent: June 22, 2021Assignee: Micron Technology, Inc.Inventors: Edward McGlaughlin, Joseph M. Jeddeloh
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Publication number: 20210165738Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.Type: ApplicationFiled: February 12, 2021Publication date: June 3, 2021Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
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Patent number: 10922221Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.Type: GrantFiled: March 28, 2018Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
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Patent number: 10892003Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.Type: GrantFiled: August 29, 2018Date of Patent: January 12, 2021Assignee: Micron Technology, Inc.Inventor: Joseph M. Jeddeloh
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Publication number: 20200394140Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Patent number: 10817430Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: GrantFiled: October 2, 2018Date of Patent: October 27, 2020Assignee: Micron Technology, Inc.Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Publication number: 20200104263Abstract: A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.Type: ApplicationFiled: October 2, 2018Publication date: April 2, 2020Inventors: Edward C. McGlaughlin, Gary J. Lucas, Joseph M. Jeddeloh
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Patent number: 10564690Abstract: The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log.Type: GrantFiled: December 13, 2017Date of Patent: February 18, 2020Assignee: Micron Technology, Inc.Inventor: Joseph M. Jeddeloh
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Publication number: 20190324847Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Edward McGlaughlin, Joseph M. Jeddeloh
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Publication number: 20190303283Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
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Patent number: 10339005Abstract: Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example method comprises writing data in a number of stripes across a storage volume of a plurality of memory devices according to a stripe map; wherein each of the number of stripes includes a number of elements; and wherein the stripe map includes a number of stripe indexes to identify the number of stripes and a number of element identifiers to identify elements included in each of the number of stripes.Type: GrantFiled: August 29, 2017Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Edward McGlaughlin, Joseph M. Jeddeloh
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Publication number: 20180374530Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.Type: ApplicationFiled: August 29, 2018Publication date: December 27, 2018Applicant: MICRON TECHNOLOGY, INC.Inventor: Joseph M. Jeddeloh
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Patent number: 10109343Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.Type: GrantFiled: May 16, 2017Date of Patent: October 23, 2018Assignee: Micron Technology, Inc.Inventor: Joseph M. Jeddeloh
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Publication number: 20180101209Abstract: The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log.Type: ApplicationFiled: December 13, 2017Publication date: April 12, 2018Inventor: Joseph M. Jeddeloh
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Patent number: 9904489Abstract: Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received.Type: GrantFiled: January 27, 2014Date of Patent: February 27, 2018Assignee: Micron Technology, Inc.Inventor: Joseph M. Jeddeloh
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Patent number: 9874918Abstract: The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log. For example, the write look ahead information can include information about a location where data would have next been written a memory system and/or includes information about the location where data had most recently been written a memory system.Type: GrantFiled: February 18, 2015Date of Patent: January 23, 2018Assignee: Micron Technology, Inc.Inventor: Joseph M. Jeddeloh