Abstract: In one apparatus, a number of obfuscated programming instructions are equipped to self-verify whether execution of the obfuscated programming instructions is being observed. In another apparatus, a number of obfuscated programming instruction are equipped to determine whether the apparatus is being operated in a mode that supports single step execution of the obfuscated programming instructions. In yet another apparatus, a number of obfuscated programming instruction are equipped to verify whether an amount of elapsed execution time has exceeded a threshold. In yet another apparatus, a first and a second group of obfuscated programming instruction are provided to implement a first and a second tamper resistant technique respectively, with the first and the second group of programming instructions sharing a storage location for a first and a second key value corresponding to the first and the second tamper resistant technique.

Abstract: In one apparatus, a number of obfuscated programming instructions is provided to perform integrity verification on a number of other plain text programming instructions. In another apparatus, a number of obfuscated programming instructions is provided to self-verify an invocation of the obfuscated programming instructions is not originated from an intruder.

Abstract: In one apparatus, a group of plain text and obfuscated cells of programming instructions is provided to implement a descrambler that descrambles scrambled content to generate descrambled content. In another apparatus, a group of plain text and obfuscated cells of programming instructions is provided to implement an authenticator that provides appropriate authentication challenges to a scrambled content provider, and generates appropriate authentication responses to authentication challenges from the scrambled content provider. In yet another apparatus, a group of plain text and obfuscated cells of programming instructions is provided to implement an integrity verifier that performs integrity verification on a decoder. In yet another apparatus, a group of plain text and obfuscated cells of programming instructions is provided to implement a secrets holder that holds a number of secrets associated with playing scrambled contents.

Abstract: A method for encoding MPEG compatible video data for subsequent compression comprises detecting a plurality of frames of video data organized as a GOP, generating an encryption key for the GOP, and encrypting the video data using GOP-synchronized substitution, transposition, and rotation transformations that are parameterized by offsets derived from the generated encryption key.

Abstract: Basic transfer units (BTUs) of compressed video data of video images are selectively encrypted in accordance with an encryption policy to degrade the video images to at least a virtually useless state, if the selectively encrypted compressed video images were to be rendered without decryption. As a result, degradation that approximates the level provided by the total encryption approach is achieved, but requiring only a fraction of the processor cycle cost required by the total encryption approach, to decrypt and render the video images.

Abstract: A hybrid decoding module which resides on the computer system's high speed memory bus. The computer system incorporating the hybrid decoding module scheme is capable of having centrally decoded resources on the memory bus as well as resources capable of decoding memory bus addresses directly. During system initialization, or after a hard reset, the decoding logic polls each of the resources on the memory bus to determine whether the resource is a centrally decoded resource or a distributed decode resource. A table is maintained for all centrally decoded resources such that when addresses are put out by the processor during run-time, the decoding logic is capable of directing control to the centrally decoded resource. Another aspect of the present invention is implemented during the initialization of the system. When resources are polled by the decoding logic, they are also provided with an identifier which identifies the last available I/O space slot.

Abstract: A hybrid decoding module which resides on the computer system's high speed memory bus. The computer system incorporating the hybrid decoding module scheme is capable of having centrally decoded resources on the memory bus as well as resources capable of decoding memory bus addresses directly. During system initialization, or after a hard reset, the decoding logic polls each of the resources on the memory bus to determine whether the resource is a centrally decoded resource or a distributed decode resource. A table is maintained for all centrally decoded resources such that when addresses are put out by the processor during run-time, the decoding logic is capable of directing control to the centrally decoded resource. Another aspect of the present invention is implemented during the initialization of the system. When resources are polled by the decoding logic, they are also provided with an identifier which identifies the last available I/O space slot.