Patents by Inventor Joseph M. Poplawski, Jr.

Joseph M. Poplawski, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5615168
    Abstract: A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: March 25, 1997
    Assignee: International Business Machines Corporation
    Inventors: George M. Lattimore, Michael K. Ciraula, Manoj Kumar, Joseph M. Poplawski, Jr., Dieter F. Wendel, Friedrich Wernicke
  • Patent number: 5544112
    Abstract: A word line driver circuit operable for receiving address signals from a decoder circuit and for gating these address signals to be outputted as a word line signal to one or more memory cells within a RAM. The driver circuit prevents oscillations of the outputted word line signal by not allowing any internal nodes between circuit elements to have a floating potential. This function is provided by a plurality of circuit elements arranged in a unique manner so that the internal nodes are not allowed to float.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: August 6, 1996
    Assignee: International Business Machines Corporation
    Inventors: Manoj Kumar, Joseph M. Poplawski, Jr.
  • Patent number: 5467037
    Abstract: A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: November 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Manoj Kumar, George M. Lattimore, Joseph M. Poplawski, Jr.