Patents by Inventor Joseph M. PUSDESRIS

Joseph M. PUSDESRIS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processing apparatus and method for decoding program instructions in order to generate control signals for processing circuitry of the data processing apparatus
    Patent number: 9880843
    Abstract: A data processing apparatus and method for accessing operands stored within a set of registers. Instruction decoder circuitry, responsive to program instructions, generates register access control signals identifying for each program instruction which registers in the register set are to be accessed by the processing circuitry when performing the processing operation specified by that program instruction. The set of registers are logically arranged as a plurality of register groups, with each register in the set being a member of more than one register group. Each program instruction includes a register specifier field, and instruction decoder circuitry is responsive to each program instruction to determine a selected register group, and to determine one or more selected members of that selected register group. The instruction decoder circuitry then outputs register access control signals identifying the register corresponding to each selected member of the selected register group.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 30, 2018
    Assignee: The Regents of the University of Michigan
    Inventors: Joseph M Pusdesris, Trevor N Mudge, Thomas D Manville
  • DATA PROCESSING APPARATUS AND METHOD FOR DECODING PROGRAM INSTRUCTIONS IN ORDER TO GENERATE CONTROL SIGNALS FOR PROCESSING CIRCUITRY OF THE DATA PROCESSING APPARATUS
    Publication number: 20130198487
    Abstract: A data processing apparatus and method for accessing operands stored within a set of registers. Instruction decoder circuitry, responsive to program instructions, generates register access control signals identifying for each program instruction which registers in the register set are to be accessed by the processing circuitry when performing the processing operation specified by that program instruction. The set of registers are logically arranged as a plurality of register groups, with each register in the set being a member of more than one register group. Each program instruction includes a register specifier field, and instruction decoder circuitry is responsive to each program instruction to determine a selected register group, and to determine one or more selected members of that selected register group. The instruction decoder circuitry then outputs register access control signals identifying the register corresponding to each selected member of the selected register group.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 1, 2013
    Applicant: The Regents of the University of Michigan
    Inventors: Joseph M. PUSDESRIS, Trevor N. MUDGE, Thomas D. MANVILLE