Patents by Inventor Joseph M. Zelayeta

Joseph M. Zelayeta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5827777
    Abstract: A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: October 27, 1998
    Assignee: LSI Logic Corporation
    Inventors: Richard D. Schinella, Gobi R. Padmanabhan, Joseph M. Zelayeta
  • Patent number: 5799080
    Abstract: A code mechanism is provided in an integrated circuit for identifying the integrated circuit such as by serial number or for use in enabling the circuit and equipment housing the circuit. Fuses, antifuses, and programmable field effect transistors are used in an array for establishing a code. The code can be established by loading a register through the array and then reading the register. Alternatively,the contents of the register can be compared with a code provided by a user to enable the circuit. In another embodiment, a ROM is loaded with a table of encryption keys, and a user addresses the ROM by loading an address in a register or in a RAM.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: August 25, 1998
    Assignee: LSI Logic Corporation
    Inventors: Gobi R. Padmanabhan, Joseph M. Zelayeta, Visvamohan Yegnashankaran, James W. Hively, John P. Daane
  • Patent number: 5600182
    Abstract: A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.
    Type: Grant
    Filed: January 24, 1995
    Date of Patent: February 4, 1997
    Assignee: LSI Logic Corporation
    Inventors: Richard D. Schinella, Gobi R. Padmanabhan, Joseph M. Zelayeta