Patents by Inventor Joseph Macri
Joseph Macri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8892963Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.Type: GrantFiled: November 9, 2006Date of Patent: November 18, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 8661300Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.Type: GrantFiled: June 27, 2011Date of Patent: February 25, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 8301930Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.Type: GrantFiled: January 21, 2009Date of Patent: October 30, 2012Assignee: ATI Technologies, Inc.Inventors: Stephen Morein, Joseph Macri, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 8031538Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.Type: GrantFiled: June 26, 2009Date of Patent: October 4, 2011Assignee: ATI Technologies ULCInventors: Joseph Macri, Olge Drapkin, Grigori Temkine, Osamu Nagashima
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Patent number: 7996731Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.Type: GrantFiled: November 1, 2006Date of Patent: August 9, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 7934109Abstract: Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.Type: GrantFiled: April 3, 2007Date of Patent: April 26, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Steven Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 7752476Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.Type: GrantFiled: May 17, 2007Date of Patent: July 6, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Joseph Macri, Steven Morein, Ming-Ju E. Lee, Lin Chen
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Patent number: 7688925Abstract: An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.Type: GrantFiled: August 1, 2005Date of Patent: March 30, 2010Assignee: ATI Technologies, Inc.Inventors: Edward Lee, Arvind Bomdica, Lin Chen, Claude Gauthier, Sam Huynh, Hiok-Tiaq Ng, John Ling, Jennifer Ho, Siji Menokki Kandiyil, Gin Yee, Joseph Macri
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Publication number: 20090323437Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.Type: ApplicationFiled: June 26, 2009Publication date: December 31, 2009Inventors: Joseph Macri, Olge Drapkin, Grigori Temkine, Osamu Nagashima
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Patent number: 7567467Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.Type: GrantFiled: October 15, 2004Date of Patent: July 28, 2009Assignee: ATI Technologies, ULCInventors: Joseph Macri, Olge Drapkin, Grigori Temkine, Osamu Nagashima
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Publication number: 20090125747Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.Type: ApplicationFiled: January 21, 2009Publication date: May 14, 2009Applicant: ATI TECHNOLOGIES, INC.Inventors: Stephen Morein, Joseph Macri, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 7509515Abstract: A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.Type: GrantFiled: September 19, 2005Date of Patent: March 24, 2009Assignee: ATI Technologies, Inc.Inventors: Joseph Macri, Steven Morein, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Patent number: 7487378Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.Type: GrantFiled: September 19, 2005Date of Patent: February 3, 2009Assignee: ATI Technologies, Inc.Inventors: Stephen Morein, Joseph Macri, Claude Gauthier, Ming-Ju E. Lee, Lin Chen
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Publication number: 20080080298Abstract: In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals may have second and third frequencies, respectively, that are about equal to the first frequency. The second and third frequencies may be out of phase relative to each other. A controller may output a first data in response to a rising edge of the second clock signal and output a second data in response to another rising edge of the third clock signal.Type: ApplicationFiled: August 30, 2007Publication date: April 3, 2008Inventor: Joseph Macri
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Publication number: 20080005455Abstract: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.Type: ApplicationFiled: May 17, 2007Publication date: January 3, 2008Inventors: Joseph Macri, Steven Morein, Ming-Ju Lee, Lin Chen
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Publication number: 20070288781Abstract: Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.Type: ApplicationFiled: April 3, 2007Publication date: December 13, 2007Inventors: Joseph Macri, Steven Morein, Claude Gauthier, Ming-Ju Lee, Lin Chen
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Publication number: 20070110205Abstract: A system includes a first communication device and a second communication device. The first communication device includes a programmable region. The programmable region of the first communication device is programmed so that an associated signal includes a number of preamble cycles. The second communication device also can include a programmable region. The programmable region of the second communication device can be programmed so that an associated signal includes a number of preamble cycles. The number of preamble cycles can be based on a variety of factors, such as the topology or implementation of the system. In an embodiment, the number of preamble cycles is associated with a data strobe signal, and data is not read or written in response to the data strobe signal until all of the preamble cycles have been transmitted and received.Type: ApplicationFiled: November 14, 2005Publication date: May 17, 2007Inventors: Joseph Macri, Mark Frankovich
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Publication number: 20070104327Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.Type: ApplicationFiled: November 9, 2006Publication date: May 10, 2007Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju Lee, Lin Chen
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Publication number: 20070101073Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.Type: ApplicationFiled: February 22, 2006Publication date: May 3, 2007Inventors: Joseph Macri, Stephen Morein, Ming-Ju Lee, Lin Chen
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Publication number: 20070098163Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.Type: ApplicationFiled: November 1, 2006Publication date: May 3, 2007Inventors: Joseph Macri, Stephen Morein, Claude Gauthier, Ming-Ju Lee, Lin Chen