Patents by Inventor Joseph Menezes
Joseph Menezes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848552Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: GrantFiled: May 6, 2022Date of Patent: December 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Publication number: 20230119625Abstract: An air purifier may include an ambient air intake configured to draw ambient air into the air purifier; a plasma reactor configured to generate one or more reaction products from the ambient air; a main body including at least the plasma reactor; a neutralizing trap configured to neutralize at least a portion of the one or more reaction products generated by the plasma reactor, thereby producing a purified gas stream; and a purified gas outlet configured to expel the purified gas stream from the air purifier. The ambient air intake may be fluidly coupled to the plasma reactor. The plasma reactor may be fluidly coupled to the neutralizing trap. The neutralizing trap may be fluidly coupled to the purified gas outlet.Type: ApplicationFiled: March 19, 2021Publication date: April 20, 2023Inventors: Tejasvi Chunduri, Volodymyr Ivanovich Golota, Abhishek Nagesh Kumbhar, Ruslan Joseph Menezes, Sujeet Shyamsunder Shinde, Raj Siman Swamy Naidu Ugapathy, Pravansu S. Mohanty
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Publication number: 20220263309Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: ApplicationFiled: May 6, 2022Publication date: August 18, 2022Inventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Patent number: 11355918Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: GrantFiled: October 23, 2020Date of Patent: June 7, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Publication number: 20220108203Abstract: In a memory device, a static random access memory (SRAM) circuit includes an array of SRAM cells arranged in rows and columns and configured to store data. The SRAM array is configured to: store a first set of information for a machine learning (ML) process in a lookup table in the SRAM array; and consecutively access, from the lookup table, information from a selected set of the SRAM cells along a row of the SRAM cells. A memory controller circuit is configured to select the set of the SRAM cells based on a second set of information for the ML process.Type: ApplicationFiled: October 1, 2020Publication date: April 7, 2022Inventors: Mahesh Madhukar MEHENDALE, Vinod Joseph MENEZES
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Patent number: 11239831Abstract: In an example, an apparatus includes a level-shifting circuit and a ramp detector. The level-shifting circuit has a current choke and a transistor coupled across the current choke, the level-shifting circuit adapted to be coupled to a first voltage source. The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, the ramp detector adapted to be coupled to a second voltage source.Type: GrantFiled: April 16, 2021Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sundeep Lakshmana Javvaji, Vinod Joseph Menezes, Jayateerth Pandurang Mathad
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Publication number: 20210409010Abstract: In an example, an apparatus includes a level-shifting circuit and a ramp detector. The level-shifting circuit has a current choke and a transistor coupled across the current choke, the level-shifting circuit adapted to be coupled to a first voltage source. The ramp detector has a ramp detector input adapted to be coupled to the first voltage source and a ramp detector output coupled to the transistor, the ramp detector adapted to be coupled to a second voltage source.Type: ApplicationFiled: April 16, 2021Publication date: December 30, 2021Inventors: Sundeep Lakshmana JAVVAJI, Vinod Joseph MENEZES, Jayateerth Pandurang MATHAD
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Patent number: 11190105Abstract: An electronic device having multiple power output circuits that individually include a switch control input, a bypass control input, an output transistor and an output control circuit that includes an RC circuit with a resistor and a capacitor coupled to the output transistor gate and a bypass switch in parallel with the RC circuit resistor. The electronic device includes a controller that selects one of the power output circuits for a given power transfer cycle, closes the bypass switch to bypass the resistor of the selected power output circuit and turns the output transistor of the selected power output circuit on to transfer current from the inductor to a load of the selected power output circuit.Type: GrantFiled: December 11, 2020Date of Patent: November 30, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vipul Kumar Singhal, RR Manikandan, Rajat Chauhan, Vinod Joseph Menezes
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Patent number: 10937470Abstract: A computer-implemented method is provided for automatically masking data for display in a mobile computing device. The computer-implemented method includes receiving a request to display data on the mobile computing device and detecting a physical location of the mobile computing device, a time corresponding to the request, and at least one network characteristic of a wireless network on which the mobile computing device is making the request. The method also includes automatically determining whether to mask the data for display in the mobile computing device based on the physical location, the time, and the at least one network characteristic. The method further includes responsive to determining to mask the data, applying one or more masking rules to the data.Type: GrantFiled: January 10, 2018Date of Patent: March 2, 2021Assignee: FMR LLCInventors: Nilesh Goel, Samir Kakkar, Meenakshi Ashokkumar, Joseph Menezes, Dhiman Dasgupta
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Patent number: 10938979Abstract: Methods and apparatuses are described for generating and displaying custom-selected content for a mobile application. A mobile device captures a request to launch an application and determines content cards eligible to be displayed. A user-specific content classification model is generated for selecting one of the content cards to be displayed, where the mobile device identifies historical usage characteristics and transmits the historical usage characteristics to a server, which generates the user-specific content classification model based upon the historical usage characteristics and transmits the user-specific content classification model to the mobile device. The mobile device executes the user-specific content classification model to select one or more content cards to be displayed and launches the application to display the selected content cards.Type: GrantFiled: March 11, 2020Date of Patent: March 2, 2021Assignee: FMR LLCInventors: Neha Dave, Samir Kakkar, Vijai Kishan Radhakrishnan, Nilesh Goel, Mandeep Makkar, Joseph Menezes, Diksha Arora
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Publication number: 20210044101Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: ApplicationFiled: October 23, 2020Publication date: February 11, 2021Inventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Patent number: 10855184Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: GrantFiled: October 14, 2019Date of Patent: December 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vinod Joseph Menezes, Manikandan Rr, Rajat Chauhan, Vipul Kumar Singhal, Mahesh Madhukar Mehendale, Kaichien Tsai
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Patent number: 10855069Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: GrantFiled: April 17, 2018Date of Patent: December 1, 2020Assignee: Texas Instruments IncorporatedInventors: Rajdeep Mukhopadhyay, Pulkit Shah, Vinod Joseph Menezes
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Publication number: 20200204075Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: ApplicationFiled: October 14, 2019Publication date: June 25, 2020Inventors: Vinod Joseph MENEZES, Manikandan RR, Rajat CHAUHAN, Vipul Kumar SINGHAL, Mahesh Madhukar MEHENDALE, Kaichien TSAI
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Patent number: 10601408Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.Type: GrantFiled: April 13, 2018Date of Patent: March 24, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajat Chauhan, Vipul Kumar Singhal, Vinod Joseph Menezes, Mahesh Madhukar Mehendale
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Publication number: 20190319447Abstract: A USB Type-C/Power Delivery controller chip includes a first pin for receiving a first voltage, a second pin for receiving a second voltage, and a third pin for coupling to the CC pin of a USB connector. The USB controller chip includes a VCONN power supply circuit having a blocking field effect transistor (BFET) coupled in series with a hot-swap field FET (HSFET) between the first and third pins, and first and second Zener diodes coupled anode-to-anode between the HSFET's source and gate. A cable detection circuit includes a BFET coupled between the second and third pins, and a Zener diode coupled between the BFET's gate and a lower rail. A power delivery physical layer circuit includes a receiver and a transmitter, each coupled to the third pin through a respective BFET, the respective BFETs each having a Zener diode coupled between respective gates and the lower rail.Type: ApplicationFiled: April 17, 2018Publication date: October 17, 2019Inventors: Rajdeep Mukhopadhyay, PuIkit Shah, Vinod Joseph Menezes
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Publication number: 20190319614Abstract: In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.Type: ApplicationFiled: April 13, 2018Publication date: October 17, 2019Inventors: Rajat Chauhan, Vipul Kumar Singhal, Vinod Joseph Menezes, Mahesh Madhukar Mehendale
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Patent number: 10447142Abstract: A switch-mode power supply includes a DC-DC converter and metering circuitry that is coupled to the DC-DC converter. The metering circuitry includes scaling circuitry, a current source, a capacitor, switching circuitry, and a comparator. The scaling circuitry is configured to generate a reference current scaled to be a predetermined fraction of a peak current flowing in an inductor of the DC-DC converter. The current source is configured to output a first current that is one-half of the reference current. The capacitor is coupled to the current source. The switching circuitry is configured to switchably connect the current source to the capacitor. The comparator is coupled to the capacitor. The comparator is configured to generate a signal indicating that a voltage across the capacitor exceeds a threshold voltage.Type: GrantFiled: December 20, 2018Date of Patent: October 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vinod Joseph Menezes, Manikandan RR, Rajat Chauhan, Vipul Kumar Singhal, Mahesh Madhukar Mehendale, Kaichien Tsai
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Publication number: 20190214060Abstract: A computer-implemented method is provided for automatically masking data for display in a mobile computing device. The computer-implemented method includes receiving a request to display data on the mobile computing device and detecting a physical location of the mobile computing device, a time corresponding to the request, and at least one network characteristic of a wireless network on which the mobile computing device is making the request. The method also includes automatically determining whether to mask the data for display in the mobile computing device based on the physical location, the time, and the at least one network characteristic. The method further includes responsive to determining to mask the data, applying one or more masking rules to the data.Type: ApplicationFiled: January 10, 2018Publication date: July 11, 2019Inventors: Nilesh Goel, Samir Kakkar, Meenakshi Ashokkumar, Joseph Menezes, Dhiman Dasgupta
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Patent number: 9218892Abstract: Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.Type: GrantFiled: June 10, 2014Date of Patent: December 22, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dharin N. Shah, Sharad Gupta, Vinod Joseph Menezes, Vish Visvanathan