Abstract: A switched inductor DC-DC power converter chiplet includes a CMOS power switch, an LC filter, regulation circuitry, feedback control circuitry, and interface control circuitry integrated on a common substrate. The inductor for the LC filter can be formed on the same surface or on opposing surfaces of the substrate as the electrical terminations for the substrate. Another embodiment includes a switched inductor DC-DC power converter chiplet having a first powertrain phase and multiple second powertrain phases. When the load current is less than or equal to a threshold load current, the power conversion efficiency can be improved by only operating the first powertrain phase. When the load current is greater than the threshold load current, the power conversion efficiency can be improved by operating one or more second powertrain phases.

Abstract: A power management module comprises one or more power converter chips that are mounted on a power management package substrate. First and second electrical contacts are disposed on opposing first and second sides of the power management package substrate. The power management module can be mounted on a processor module to supply power to one or more processor chips in the processor module. In one example, the processor chip(s) are mounted on a first side of a processor package substrate and the power management module is mounted on an opposing second side of the processor package substrate. The power management module and the processor module can be centered and aligned with respect to each other or they can be offset laterally from each other. In another embodiment, the processor chip(s) are embedded in the processor package substrate.

Abstract: A power management module comprises one or more power converter chips that are mounted on a power management package substrate. First and second electrical contacts are disposed on opposing first and second sides of the power management package substrate. The power management module can be mounted on a processor module to supply power to one or more processor chips in the processor module. In one example, the processor chip(s) are mounted on a first side of a processor package substrate and the power management module is mounted on an opposing second side of the processor package substrate. The power management module and the processor module can be centered and aligned with respect to each other or they can be offset laterally from each other. In another embodiment, the processor chip(s) are embedded in the processor package substrate.

Abstract: A power management module comprises one or more power converter chips that are mounted on a power management package substrate. First and second electrical contacts are disposed on opposing first and second sides of the power management package substrate. The power management module can be mounted on a processor module to supply power to one or more processor chips in the processor module. In one example, the processor chip(s) are mounted on a first side of a processor package substrate and the power management module is mounted on an opposing second side of the processor package substrate. The power management module and the processor module can be centered and aligned with respect to each other or they can be offset laterally from each other. In another embodiment, the power management module and the processor chip(s) are mounted on the same side of the processor package substrate.

Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

Abstract: A switched inductor DC-DC power converter chiplet includes a CMOS power switch, an LC filter, regulation circuitry, feedback control circuitry, and interface control circuitry integrated on a common substrate. The inductor for the LC filter can be formed on the same surface or on opposing surfaces of the substrate as the electrical terminations for the substrate. Another embodiment includes a switched inductor DC-DC power converter chiplet having a first powertrain phase and multiple second powertrain phases. When the load current is less than or equal to a threshold load current, the power conversion efficiency can be improved by only operating the first powertrain phase. When the load current is greater than the threshold load current, the power conversion efficiency can be improved by operating one or more second powertrain phases.

Abstract: A switched inductor DC-DC power converter chiplet includes a CMOS power switch, an LC filter, regulation circuitry, feedback control circuitry, and interface control circuitry integrated on a common substrate. The inductor for the LC filter can be formed on the same surface or on opposing surfaces of the substrate as the electrical terminations for the substrate.

Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

Abstract: A switched-mode power converter includes timing control feedback loop circuits to minimize or eliminate the potential difference across a high-power switch and a low-power switch during their transitions times. A first feedback circuit compares the measured voltage across the high-power switch at the moment the high-power switch closes with the input voltage to the high-power switch to control a low-to-high delay time. A second feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch closes with the input voltage to the low-power switch to control a high-to-low delay time. A third feedback circuit compares the measured voltage across the low-power switch at the moment the low-power switch opens. The output of the third feedback circuit is provided as inputs to the first and second feedback circuits. The third feedback circuit also controls the frequency of the power converter.

Abstract: Bottle (10) for storage and transfer with dual compartments (11 and 12) separated during storage by a movable intermediate seal (13). The bottle (10) also has a narrow neck (15) in which a sealing device engages comprising an elastomeric sealing member (61) and a capsule (17) attached to said member. The capsule extends toward the outside into a tip (18) in which there is a closing valve (63) urged by a spring (62) which supports a disc (60b) of a rigid element (60) attached to the inside of the sealing member (61).

Abstract: A mask which is resistant to a plasma etching treatment is formed by providing an etch resistant skin over a lithographically patterned radiation sensitive resist film present on a substrate. The etch resistant skin is formed by providing a layer of, for example, chromium on the patterned resist and on the exposed surface of the substrate, and then, baking so that the chromium reacts chemically with the resist to form the etch resistant skin around the patterned film. This method may be used for example to manufacture a photo mask using a chromium coated glass substrate, or during the manufacture of semiconductor devices on a semiconductor wafer substrate.

Abstract: A mask which is resistant to a plasma etching treatment is formed by lithographically patterning a radiation sensitive film present on a substrate. The etch resistance of the mask is enhanced by exposure to a carbon monoxide plasma which forms a region with an enhanced etch resistance over the surface of the patterned film. This method may be used, for example, to manufacture a photomask using a chromium coated glass substrate, or during the manufacture of semiconductor devices on a semiconductor wafer substrate.