Patents by Inventor Joseph Michael Bulger

Joseph Michael Bulger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer
    Patent number: 10911020
    Abstract: A wafer-level chip-scale package includes a polymeric body having a conductive via passing through the polymeric body and a piezoelectric substrate directly bonded to an upper end of the conductive via. The wafer-level chip-scale package further includes a cavity defined between a portion of the polymeric body and the piezoelectric substrate and a metal seal ring disposed in the body and having an upper end bonded to the piezoelectric substrate, the metal seal ring passing only partially through the body.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: February 2, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Joseph Michael Bulger
  • METHOD OF PROVIDING PROTECTIVE CAVITY AND INTEGRATED PASSIVE COMPONENTS IN WAFER LEVEL CHIP SCALE PACKAGE USING A CARRIER WAFER
    Publication number: 20200144985
    Abstract: A wafer-level chip-scale package includes a polymeric body having a conductive via passing through the polymeric body and a piezoelectric substrate directly bonded to an upper end of the conductive via. The wafer-level chip-scale package further includes a cavity defined between a portion of the polymeric body and the piezoelectric substrate and a metal seal ring disposed in the body and having an upper end bonded to the piezoelectric substrate, the metal seal ring passing only partially through the body.
    Type: Application
    Filed: January 2, 2020
    Publication date: May 7, 2020
    Inventor: Joseph Michael Bulger
  • Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer
    Patent number: 10559741
    Abstract: A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: February 11, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Joseph Michael Bulger
  • METHOD OF PROVIDING PROTECTIVE CAVITY AND INTEGRATED PASSIVE COMPONENTS IN WAFER LEVEL CHIP SCALE PACKAGE USING A CARRIER WAFER
    Publication number: 20190305750
    Abstract: A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.
    Type: Application
    Filed: June 19, 2019
    Publication date: October 3, 2019
    Inventor: Joseph Michael Bulger
  • Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer
    Patent number: 10374574
    Abstract: A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 6, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Joseph Michael Bulger
  • METHOD OF PROVIDING PROTECTIVE CAVITY AND INTEGRATED PASSIVE COMPONENTS IN WAFER LEVEL CHIP SCALE PACKAGE USING A CARRIER WAFER
    Publication number: 20170163243
    Abstract: A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 8, 2017
    Inventor: Joseph Michael Bulger