Patents by Inventor Joseph N. Merrett

Joseph N. Merrett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7556994
    Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: July 7, 2009
    Assignee: SemiSouth Laboratories, Inc.
    Inventors: Igor Sankin, Joseph N. Merrett
  • Patent number: 7510921
    Abstract: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: March 31, 2009
    Assignee: SemiSouth Laboratories, Inc.
    Inventors: Igor Sankin, Janna B. Casady, Joseph N. Merrett
  • Patent number: 7470967
    Abstract: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: December 30, 2008
    Assignee: SemiSouth Laboratories, Inc.
    Inventors: Igor Sankin, Janna B. Casady, Joseph N. Merrett
  • Patent number: 7416929
    Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: August 26, 2008
    Assignees: SemiSouth Laboratories, Inc., Mississippi State University
    Inventors: Michael S. Mazzola, Joseph N. Merrett
  • Patent number: 7294860
    Abstract: A switching element combining a self-aligned, vertical junction field effect transistor with etched-implanted gate and an integrated antiparallel Schottky barrier diode is described. The anode of the diode is connected to the source of the transistor at the device level in order to reduce losses due to stray inductances. The SiC surface in the SBD anode region is conditioned through dry etching to achieve a low Schottky barrier height so as to reduce power losses associated with the turn on voltage of the SBD.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: November 13, 2007
    Assignees: Mississippi State University, SemiSouth Laboratories, Inc.
    Inventors: Michael S. Mazzola, Joseph N. Merrett
  • Patent number: 7242040
    Abstract: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: July 10, 2007
    Assignee: Semisouth Laboratories, Inc.
    Inventors: Igor Sankin, Jeffrey B. Casady, Joseph N. Merrett
  • Patent number: 7202528
    Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: April 10, 2007
    Assignee: Semisouth Laboratories, Inc.
    Inventors: Igor Sankin, Joseph N. Merrett
  • Patent number: 7119380
    Abstract: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: October 10, 2006
    Assignee: SemiSouth Laboratories, Inc.
    Inventors: Igor Sankin, Jeffrey B. Casady, Joseph N. Merrett