Patents by Inventor Joseph Nagel
Joseph Nagel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10461251Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.Type: GrantFiled: August 21, 2018Date of Patent: October 29, 2019Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sanjeev Aggarwal, Sarin A. Deshpande, Kerry Joseph Nagel
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Patent number: 10461250Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.Type: GrantFiled: July 31, 2018Date of Patent: October 29, 2019Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
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Patent number: 10396279Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.Type: GrantFiled: August 2, 2018Date of Patent: August 27, 2019Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
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Publication number: 20190140167Abstract: A method of fabricating an integrated circuit device includes forming a trench in a dielectric material and forming a ferromagnetic circuit element having an angled surface on the trench. The angled surface of the circuit element is removed using a chemical mechanical polishing (CMP) process and the trench is filled with an electrically conductive material.Type: ApplicationFiled: October 30, 2018Publication date: May 9, 2019Applicant: Everspin Technologies, Inc.Inventors: Sanjeev AGGARWAL, Kerry Joseph Nagel
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Publication number: 20190140019Abstract: An integrated circuit device includes a memory portion and a logic portion. The memory portion may include a plurality of magnetoresistive devices and the logic portion may include logic circuits. The memory portion may include a plurality of metal conductors separated by a first interlayer dielectric material (ILD), wherein the first ILD is a low-k ILD or an ultra low-k ILD. And, the logic portion may include a plurality of metal conductors separated by a second interlayer dielectric material (ILD).Type: ApplicationFiled: November 8, 2018Publication date: May 9, 2019Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Sarin A. DESHPANDE
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Publication number: 20190103555Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: ApplicationFiled: November 19, 2018Publication date: April 4, 2019Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Kenneth H. SMITH, Moazzem HOSSAIN, Sanjeev AGGARWAL
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Publication number: 20190103554Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.Type: ApplicationFiled: August 21, 2018Publication date: April 4, 2019Applicant: Everspin Technologies, Inc.Inventors: Sanjeev AGGARWAL, Sarin A. Deshpande, Kerry Joseph Nagel
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Publication number: 20190067566Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.Type: ApplicationFiled: August 22, 2018Publication date: February 28, 2019Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Sarin A. DESHPANDE
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Publication number: 20190043921Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.Type: ApplicationFiled: September 26, 2018Publication date: February 7, 2019Applicant: Everspin Technologies, Inc.Inventors: Thomas ANDRE, Sanjeev AGGARWAL, Kerry Joseph NAGEL, Sarin A. DESHPANDE
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Publication number: 20180375018Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.Type: ApplicationFiled: July 31, 2018Publication date: December 27, 2018Applicant: Everspin Technologies, Inc.Inventors: Sarin A. DESHPANDE, Kerry Joseph NAGEL, Chaitanya MUDIVARTHI, Sanjeev AGGARWAL
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Patent number: 10164176Abstract: A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material.Type: GrantFiled: January 6, 2017Date of Patent: December 25, 2018Assignee: Everspin Technologies, Inc.Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
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Publication number: 20180342670Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.Type: ApplicationFiled: August 2, 2018Publication date: November 29, 2018Applicant: Everspin Technologies, Inc.Inventors: Sarin A. DESHPANDE, Sanjeev AGGARWAL, Kerry Joseph NAGEL
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Patent number: 10103197Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.Type: GrantFiled: July 14, 2017Date of Patent: October 16, 2018Assignee: Everspin Technologies, Inc.Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
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Patent number: 10079339Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.Type: GrantFiled: October 9, 2017Date of Patent: September 18, 2018Assignee: Everspin Technologies, Inc.Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
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Patent number: 10062839Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.Type: GrantFiled: December 27, 2017Date of Patent: August 28, 2018Assignee: Everspin Technologies, Inc.Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
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Publication number: 20180145248Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.Type: ApplicationFiled: December 27, 2017Publication date: May 24, 2018Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
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Publication number: 20180138396Abstract: Techniques are presented for ensuring alignment marks are available for use and patterning magnetoresistive devices following the deposition of layers used to form the magnetoresistive devices. In some cases, the plurality of layers corresponding to the magnetoresistive devices are selectively etched in order to expose the underlying alignment marks, whereas in other embodiments, the deposition of the plurality of layers is controlled by deposition tool tabs that prevent the materials from obscuring the underlying alignment marks.Type: ApplicationFiled: November 10, 2017Publication date: May 17, 2018Applicant: Everspin Technologies, Inc.Inventor: Kerry Joseph Nagel
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Publication number: 20180033959Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.Type: ApplicationFiled: October 9, 2017Publication date: February 1, 2018Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
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Patent number: 9865804Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask over a selected portion of the third layer of ferromagnetic material, wherein the mask is a metal hard mask. Thereafter, etching through the third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure, through the second tunnel barrier layer to form a second tunnel barrier and provide sidewalls thereof and the second layer of ferromagnetic material to provide sidewalls thereof. Thereafter, etching, through the first tunnel barrier layer to form a first tunnel barrier to provide sidewalls thereof and etching the first layer of ferromagnetic material to provide sidewalls thereof. The process may then include oxidizing the sidewalls of (i) the first tunnel barrier and (ii) the first layer of ferromagnetic material.Type: GrantFiled: June 22, 2017Date of Patent: January 9, 2018Assignee: Everspin Technologies, Inc.Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel
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Patent number: 9793470Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching (i) the first encapsulation layer which is disposed over the exposed surface of the dielectric layer and (ii) re-deposited material disposed on the dielectric layer, wherein, thereafter a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region. The method further includes depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer; and etching the remaining layers of the stack/structure (via one or more etch processes).Type: GrantFiled: February 2, 2016Date of Patent: October 17, 2017Assignee: Everspin Technologies, Inc.Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal