Patents by Inventor Joseph Neil Greeley
Joseph Neil Greeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9666801Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.Type: GrantFiled: May 16, 2016Date of Patent: May 30, 2017Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, John Smythe, Bhaskar Srinivasan, Gurtej S. Sandhu, Joseph Neil Greeley, Kunal R. Parekh
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Publication number: 20160260899Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.Type: ApplicationFiled: May 16, 2016Publication date: September 8, 2016Applicant: Micron Technology, Inc.Inventors: Nishant Sinha, John Smythe, Bhaskar Srinivasan, Gurtej S. Sandhu, Joseph Neil Greeley, Kunal R. Parekh
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Publication number: 20160203993Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
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Patent number: 9343665Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.Type: GrantFiled: July 2, 2008Date of Patent: May 17, 2016Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, John Smythe, Bhaskar Srinivasan, Gurtej S. Sandhu, Joseph Neil Greeley, Kunal R. Parekh
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Publication number: 20160013263Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.Type: ApplicationFiled: September 22, 2015Publication date: January 14, 2016Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
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Patent number: 9236427Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.Type: GrantFiled: September 30, 2014Date of Patent: January 12, 2016Assignee: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
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Patent number: 9159780Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.Type: GrantFiled: January 14, 2015Date of Patent: October 13, 2015Assignee: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
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Publication number: 20150128992Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.Type: ApplicationFiled: January 26, 2015Publication date: May 14, 2015Inventors: Joseph Neil Greeley, Dan Millward, Wayne Huang
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Publication number: 20150126016Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.Type: ApplicationFiled: January 14, 2015Publication date: May 7, 2015Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
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Publication number: 20150054127Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
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Patent number: 8946043Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.Type: GrantFiled: December 21, 2011Date of Patent: February 3, 2015Assignee: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
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Patent number: 8865544Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.Type: GrantFiled: July 11, 2012Date of Patent: October 21, 2014Assignee: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
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Publication number: 20140015097Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.Type: ApplicationFiled: July 11, 2012Publication date: January 16, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
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Patent number: 8513135Abstract: Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of material.Type: GrantFiled: September 27, 2011Date of Patent: August 20, 2013Assignee: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Paul Morgan, Mark Kiehlbauch
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Publication number: 20130164902Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
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Publication number: 20120015520Abstract: Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of material.Type: ApplicationFiled: September 27, 2011Publication date: January 19, 2012Inventors: Joseph Neil Greeley, Paul Morgan, Mark Kiehlbauch
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Patent number: 8026180Abstract: Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of material.Type: GrantFiled: July 12, 2007Date of Patent: September 27, 2011Assignee: Micron Technology, Inc.Inventors: Joseph Neil Greeley, Paul Morgan, Mark Kiehlbauch
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Publication number: 20090017627Abstract: Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of material.Type: ApplicationFiled: July 12, 2007Publication date: January 15, 2009Inventors: Joseph Neil Greeley, Paul Morgan, Mark Kiehlbauch