Patents by Inventor Joseph Nicolas Kozhaya

Joseph Nicolas Kozhaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8775996
    Abstract: A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Joseph Nicolas Kozhaya, Zhuo Li, Joseph J. Palumbo, Haifeng Qian, Phillip John Restle, Chin Ngai Sze, Ying Zhou
  • Publication number: 20140143746
    Abstract: A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles Jay Alpert, Joseph Nicolas Kozhaya, Zhuo Li, Joseph J. Palumbo, Haifeng Qian, Phillip John Restle, Chin Ngai Sze, Ying Zhou
  • Patent number: 8677305
    Abstract: An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Joseph Nicolas Kozhaya, Zhuo Li, Joseph J Palumbo, Haifeng Qian, Phillip John Restle, Chin Ngai Sze, Ying Zhou
  • Publication number: 20130326456
    Abstract: An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 5, 2013
    Applicant: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Joseph Nicolas Kozhaya, Zhuo Li, Joseph J Palumbo, Haifeng Qian, Phillip John Restle, Chin Ngai Sze, Ying Zhou