Patents by Inventor JOSEPH O. LIU

JOSEPH O. LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387036
    Abstract: A method includes performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer. The method also includes performing a wafer expansion process that separates individual semiconductor dies from the wafer after the laser ablation process.
    Type: Application
    Filed: May 27, 2022
    Publication date: November 30, 2023
    Inventors: Michael Todd Wyant, Joseph O. Liu, Christopher Daniel Manack
  • Publication number: 20230260839
    Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, CHRISTOPHER DANIEL MANACK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO, MING ZHU, JOSEPH O. LIU
  • Publication number: 20230253251
    Abstract: A method of manufacturing a semiconductor package includes forming a plurality of first cuts in a semiconductor wafer. The first cuts extend through a first portion of a thickness of the semiconductor wafer and include a first set of first cuts that are parallel to one another and a second set of first cuts that are parallel to one another and perpendicular to the first set of first cuts. In addition, the method includes forming a plurality of second cuts in the wafer after forming the first cuts. The second cuts are vertically aligned with the first cuts and extend through a second portion of the thickness of the semiconductor wafer.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Inventors: Qing Ran, Yang Liu, Joseph O. Liu
  • Publication number: 20230170257
    Abstract: A method of dicing a wafer includes positioning the wafer with its top side on a tape material. The wafer includes a plurality of die separated by scribe streets. A first pass being a first infrared (IR) laser beam is directed at the bottom side with a point of entry within the scribe streets. The first IR laser beam is focused with a focus point embedded within a thickness of the wafer, and has parameters selected to form an embedded crack line within the wafer. The embedded crack line does not reach the top side surface. A second pass being a second IR laser beam is directed at the bottom side having parameters selected to form a second crack line that that has a spacing relative to the embedded crack line, and the second IR laser beam causes the embedded crack line to be extended to the top side surface.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Yang Liu, Hao Zhang, Venkataramanan Kalyanaraman, Joseph O Liu, Qing Ran, Yuan Zhang, Gelline Joyce Untalan Vargas, Jeniffer Otero Aspuria
  • Patent number: 11664276
    Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 30, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew John Sherbin, Michael Todd Wyant, Christopher Daniel Manack, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Ming Zhu, Joseph O. Liu
  • Publication number: 20200176314
    Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, CHRISTOPHER DANIEL MANACK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO, MING ZHU, JOSEPH O. LIU