Abstract: The efficient storage of transformation information in a switch is provided. A respective port of the switch can include a memory device capable of storing transformation information. During operation, the switch can apply a selection mechanism to the transformation information learned at the switch for identifying a target port. The switch can then store the information in the memory device of the target port. Upon receiving a packet, the ingress port can apply the selection mechanism to the header information of the packet for determining a location of a first piece of transformation information associated with the packet. The ingress port can obtain the first piece of transformation information by looking up the header information in the location and storing it in a local memory device. The ingress port can then transform the packet based on the first piece of transformation information for determining an egress port for the packet.

Abstract: The efficient storage of transformation information in a switch is provided. A respective port of the switch can include a memory device capable of storing transformation information. During operation, the switch can apply a selection mechanism to the transformation information learned at the switch for identifying a target port. The switch can then store the information in the memory device of the target port. Upon receiving a packet, the ingress port can apply the selection mechanism to the header information of the packet for determining a location of a first piece of transformation information associated with the packet. The ingress port can obtain the first piece of transformation information by looking up the header information in the location and storing it in a local memory device. The ingress port can then transform the packet based on the first piece of transformation information for determining an egress port for the packet.

Abstract: The efficient storage of transformation information in a switch is provided. A respective port of the switch can include a memory device capable of storing transformation information. During operation, the switch can apply a selection mechanism to the transformation information learned at the switch for identifying a target port. The switch can then store the information in the memory device of the target port. Upon receiving a packet, the ingress port can apply the selection mechanism to the header information of the packet for determining a location of a first piece of transformation information associated with the packet. The ingress port can obtain the first piece of transformation information by looking up the header information in the location and storing it in a local memory device. The ingress port can then transform the packet based on the first piece of transformation information for determining an egress port for the packet.

Abstract: A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory location within a failed memory location. A wear-leveling rate on the memory module may be adjusted based on the remapping rate.

Abstract: A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory location within a failed memory location. A wear-leveling rate on the memory module may be adjusted based on the remapping rate.

Abstract: Array based memory abstraction in a multiprocessor computing system is disclosed. A plurality of memory resources are operably connected to an interconnect fabric. In a plurality of memory blocks, each memory block represents a contiguous portion of the plurality of memory resources. A cell is operably connected to the interconnect fabric. The cell has an agent with a fabric abstraction block, and the fabric abstraction block includes a block table having an entry for each of the plurality of memory blocks. A memory controller is associated with the agent, is operably connected to the interconnect fabric, and is configured to control a portion of the plurality of memory blocks.