Abstract: An asynchronous transfer mode (ATM) segmentation and reassembly (SAR) circuit uses a memory map which accommodates a variety of memory sizes. The SAR circuit generates address signals according to the memory map which is independent of memory size. The most significant bits (MSBs) of the address are ignored for memories having fewer address terminals than the SAR circuit. The memory map allocates N-bit addresses to buffers and an expansion area. A first buffer has addresses with i+1 MSBs set to 1 and a second buffer has addresses with i+1 MSBs set to 0. i MSBs can be ignored without causing address conflicts because an address for the first buffer has at least one bit that differs from a corresponding bit in an address for the second buffer. The first and second buffers expand, as required, into the expansion area between the buffer. For an application using the smallest memory, conflicts do not occur because the first and second buffers are sufficient for the minimum memory applications.

Abstract: A plurality of parallel single port memory arrays are coupled between a corresponding plurality of input FIFO sets and a corresponding plurality of output FIFO sets to create a high-speed FIFO memory device. The input FIFO sets, which provide data values to their corresponding single port memory arrays, are responsive to a write clock signal. The output FIFO sets, which receive data values from their corresponding single port memory arrays, are responsive to a read clock signal. The order of read and write operations within each single port memory array is controlled by a corresponding state machine which is coupled to either the write clock signal or the read clock signal. Each of the parallel single port memory arrays operates independently. The input FIFO sets de-interleave an input data stream into a plurality of intermediate data streams. Each intermediate data stream is routed through a single port memory array to an output FIFO set.

Abstract: A plurality of parallel single port memory arrays are coupled between a corresponding plurality of input FIFO sets and a corresponding plurality of output FIFO sets to create a high-speed FIFO memory device. The input FIFO sets, which provide data values to their corresponding single port memory arrays, are responsive to a write clock signal. The output FIFO sets, which receive data values from their corresponding single port memory arrays, are responsive to a read clock signal. The order of read and write operations within each single port memory array is controlled by a corresponding state machine which is coupled to either the write clock signal or the read clock signal. Each of the parallel single port memory arrays operates independently. The input FIFO sets de-interleave an input data stream into a plurality of intermediate data streams. Each intermediate data stream is routed through a single port memory array to an output FIFO set.