Abstract: A method for improving the quality of healthcare, efficiency, and patient satisfaction procedures is provided. The method includes conducting at least a first survey of patients regarding care provided before, during, and after a procedure, wherein the survey focuses on benchmarks identified as being relevant to quality of care. The method further includes entering the results of the first survey into a database configured to store the results, reviewing the results of the first survey to determine the quality of care provided during the procedure, identifying incidences of poor quality of care, and comparing the results of the first survey with results of surveys taken from other patients to recognize patterns of poor quality of care. The method further includes addressing the incidences of poor quality of care by developing methods to address the recognized incidences of poor quality of care.

Abstract: A method for improving the quality of healthcare, efficiency, and patient satisfaction procedures is provided. The method includes conducting at least a first survey of patients regarding care provided before, during, and after a procedure, wherein the survey focuses on benchmarks identified as being relevant to quality of care. The method further includes entering the results of the first survey into a database configured to store the results, reviewing the results of the first survey to determine the quality of care provided during the procedure, identifying incidences of poor quality of care, and comparing the results of the first survey with results of surveys taken from other patients to recognize patterns of poor quality of care. The method further includes addressing the incidences of poor quality of care by developing methods to address the recognized incidences of poor quality of care.

Abstract: A method includes: obtaining answers to a plurality of predetermined questions from at least one person, the questions relating to a situation in which an enterprise provides a client with offerings that include at least one of a product and a service; and utilizing the answers to at least some of the questions to prepare a report, including identifying within the report areas of past innovation within the enterprise with respect to the offerings, and areas currently appropriate for innovation within the enterprise with respect to the offerings. The method can be implemented in the form of a computer program stored on a computer-readable medium.

Abstract: Bus testing logic is built into some of the devices connected to the bus to enable these devices to perform diagnostic testing of the bus. Under control of the test logic, the devices drive the bus with output voltages corresponding to a predetermined test bit pattern that is selected to cause the bus to reach a target bus utilization level. The bus signals produced by the devices propagate along the bus and are received by other devices. The received bus signals are resolved into a received bit pattern. The received bit pattern is compared with the test bit pattern used to generate the bus signals in order to detect discrepancies. In one embodiment, the devices can operate in a first mode by driving the bus in accordance with performing normal functions or in a second mode by performing diagnostic testing on the bus by driving the bus in accordance with the test bit pattern. Test patterns can be interleaved with normal bus signals.

Abstract: A test system for testing communications over a bus connecting electronic devices, e.g., components of a computer system is preferably embedded in the devices themselves rather than in apparatus external to them, and is responsive to digital control signals, e.g., conforming to JTAG, for scanning test data into and out of the devices. The test system has a stress injection module for injecting a set of stimulus patterns on the bus; an error identification module for identifying an error resulting from the set of stimulus patterns; a bus tuning module for adjusting one or more bus operating and signaling parameters so that testing can be performed at one or more of a number of different sets of operating and signaling parameters; a programmable control module for controlling the bus tuning module; and a presentation module for presenting a plurality of results of the testing.

Abstract: A system for programmatically adjusting electrical characteristics of a bus interface so as to modify bus operating and signaling parameters employs a control module or mechanism, responsive to a digital signal, for setting the characteristic's value. The electrical characteristic can be a voltage determinative, for example, of any of the following bus operating and signaling parameters: driver output rise time, driver output fall time, driver voltage limits, driver propagation time, receiver threshold voltage levels, or termination resistance. The digital signal can be generated, for example, by a computer-executable program, a controller, or other such device, that applies the digital signal to the control mechanism, for example, via a JTAG interface/controller.

Abstract: Testing of an electronic system is optimized by using a single set of sub-tests and varying the testing sequence to produce tests tailored for different purposes such as screening and diagnostic testing. For example, a programmable test sequencer in the electronic system responds to a test selection variable by using a first sequence of the sub-tests to optimize the testing process for screening and a second sequence of the sub-tests to optimize the testing process for diagnostic testing. In the diagnostic mode, the sub-tests are run so that each sub-test builds upon the previous sub-tests and uses previously-tested hardware to verify additional hardware. In the screening mode, the sub-tests are the same, but the execution order of the sub-tests is reversed so that more complex hardware is tested first as a screening mechanism.

Abstract: A bus tuning system is provided for determining the configuration of an electronic device and for testing and tuning a bus system of the electronic device specifically for its configuration, the bus system including a bus interface coupled with a bus characterized by a number of parameters.

Abstract: Information regarding the operating conditions of a computer system is stored in a storage which is dedicated to a failure management system. The storage is updated with the current operating conditions either periodically or upon the occurrence of predetermined events. When a first failure identification mechanism identifies a failure in the computer system, a capture mechanism interrupts the updating of the storage leaving information regarding operating conditions which contributed to the failure in the storage. This latter information can then be read out to aid in diagnosis of the failure. Since the operating condition information is stored in a dedicated storage, the information is not modified by events that take place after the failure is identified. In accordance with one embodiment, the computer system ordinarily holds state and other operating information in a set of storage devices, such as, for example, state registers.

Abstract: A HASS testing system provides for testing and tuning of a bus system of an electronic device having a bus interface coupled with a bus characterized by a number of parameters.

Abstract: A bus driver introduces a propagation delay of programmable duration prior to transmission of data over a bus. The bus driver has an input stage for acquiring data for transmission over a bus and an output stage having a driver circuit for transmitting data received from the input stage over the bus. The input stage has a first storage element for storing the data for a first period of time responsive to a first clock signal; and a second storage element for storing the data received from the first storage element for a second period of time whose duration is responsive to a second clock signal. The bus driver also has a programmable delay module coupled with the second storage element for regulating the second clock signal in response to a programmable digital signal and thereby regulating duration of the second period of time.

Abstract: An I/O bus into the cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination Circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell a the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. The termination further includes a circuit to linearize the impedance as a function of the reference voltage.