Abstract: A process for producing a magnetic core material is disclosed. The process includes distributing particles within a solution medium to form a colloidal solution. The process further includes modifying a surface chemistry of the particles by adding one or more additives to the colloidal solution. The process further includes gelating the colloidal solution to form the magnetic core material.

Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The substrate includes multiple capacitor regions, such as a first capacitor region and a second capacitor region that are adjacent to one another. Each capacitor region includes trenches that are formed within the substrate. A metal-insulator-metal capacitor is formed within the trenches and at least partially over the substrate. The trenches disposed within the first capacitor region are at least substantially perpendicular to the trenches disposed within the second capacitor region.

Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.

Abstract: Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.

Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

Abstract: Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed.

Abstract: A new and improved method of forming a thin film resistor is provided herein that overcomes many of the drawbacks of prior art methods. More specifically, the new method of forming a thin film provides for a well-controlled dielectric thickness under the thin film resistor which is useful for laser trimming purpose. The preferred thickness of the dielectric layer is an integer of a quarter wavelength of the optical energy used to laser trim the resistor. The new method also provides contacts to the thin film resistor that do not directly contact the thin film resistor so as to prevent any adverse process effects to the thin film resistor.

Abstract: A method of modifying a layer of thin film composite material to achieve one or more desired properties for the thin film layer which cannot be achieved by heat treatment at all practical temperatures of operation allowable by particular integrated circuit processes. In particular, the thin film composite material is subjected to an ion implantation process. Depending on the doping species, the doping concentration, the doping energy, and other ion implantation parameters, one or more properties of the deposited thin film resistive layer can be modified. Such properties may include electrical, optical, thermal and physical properties. For instance, the sheet resistance and/or the temperature coefficient of resistance of the thin film composite material may be increased or decreased by appropriately implanting ions into the material. The ion implantation can be applied globally in order to modify one or more properties of the entire deposited thin film composite layer.

Abstract: This invention relates to the design of apparatus for processing electronic devices, including equipment for chemical vapor deposition or transport polymerization. The new designs of gas separator plates, their configuration, and the regulation of gas flows through the system provides control over the pattern of precursor gas flow away from the separation plates, thereby decreasing the amount of byproducts that are deposited on the plates and throughout the reactor. New designs for shaping other surfaces of the dispersion head reduces contamination of those elements, and new designs for chamber panels decrease the deposition of byproducts on those surfaces, as well as other elements of the reactor. Decreasing deposition of byproducts increases the amount and the quality of the film that can be deposited without requiring the system to be shut down for cleaning.

Abstract: This invention relates to the design of apparatus for processing electronic devices, including equipment for chemical vapor deposition. The new designs of gas separator plates, their configuration, and the regulation of gas flows through the system provides control over the pattern of precursor gas flow away from the separation plates, thereby decreasing the amount of byproducts that are deposited on the plates and throughout the reactor. New designs for shaping other surfaces of the dispersion head reduces contamination of those elements, and new designs for chamber panels decrease the deposition of byproducts on those surfaces, as well as other elements of the reactor. Decreasing deposition of byproducts increases the amount of thin film, and the quality of the film which can be deposited without requiring the system to be shut down. This increases the throughput of products in the deposition process, thereby increasing the efficiency of electronic device manufacture and lowering the cost.

Abstract: An integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Abstract: A integrated circuit structure and a method of fabrication thereof are provided. In particular, fully planarized, trench isolated semiconductor regions, e.g. comprising doped polysilicon, are provided in an integrated circuit substrate. These polysilicon regions have a smooth surface, substantially coplanar with the substrate surface, provided by chemical mechanical polishing. The near zero topography substrate provides for formation thereon of integrated circuit structures including e.g. capacitors, resistors, thin film capacitors, and interconnects, in the polysilicon trench regions at the same process level as devices formed in the semiconductor substrate. Thus a simple and flexible process for formation of improved device structures is provided, compatible with known Bipolar, CMOS and Bipolar-CMOS processes.

Abstract: A buried layer contact for a integrated circuit structure is provided, with particular application for a contact for a buried collector of a bipolar transistor. The buried layer contact takes the form of a sinker comprising a fully recessed trench isolated structure having dielectric lined sidewalls and filled with conductive material, e.g. doped polysilicon which contacts the buried layer. The trench isolated contact is more compact than a conventional diffused sinker structure, and thus beneficially allows for reduced transistor area. Advantageously, a reduced area sinker reduces the parasitic capacitance and power dissipation. In a practical implementation, the structure provides for an annular collector contact structure to reduce collector resistance.

Abstract: A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provided around the tapered body to form base contact electrodes. The tapered body is selectively removed from the substrate without damaging the underlying silicon substrate, to leave a tapered opening; localized dielectric isolation is provided in the form of sidewall spacers on the first conductive layer. The tapered opening is filled with a layer of a second conductive material to form a second electrode i.e. an emitter structure.

Abstract: A method is provided for forming electrodes of a trench capacitor for an integrated circuit in which the number of mask levels is reduced. The method is compatible with CMOS and Bipolar CMOS processes. After defining a trench in a substrate by a conventional photoengraving step and anisotropic etching, successive conformal layers of a first dielectric layer, a first conductive layer, and subsequent conformal dielectric layers and conformal conductive layers are deposited to fill the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Each of the conductive layers form an electrode. Coplanar areas of each of the conductive layers are exposed within the trench for formation of contacts to the electrodes. Advantageously, the trench has a wide portion and a narrow portion of smaller lateral dimension.

Abstract: A method is provided for forming a fully planarized trench isolated region in a semiconductor substrate for an integrated circuit, for example, a trench isolated field oxide region, or a trench isolated semiconductor region in which thin film semiconductor devices are formed. Planarization is accomplished by a chemical mechanical polishing process in which coplanar layers of a chemical mechanical polish resistant material are provided in a centre region of wide trenches as well as on the semiconductor substrate surface adjacent the trenches. The chemical mechanical polish resistant layer in the centre region of a wide trench forms an etch stop to prevent dishing of layers filling the trench during overall wafer planarization by chemical mechanical polishing. The method is compatible with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuit structures.

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench.

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench.