Abstract: A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.

Abstract: A structure for implementing a plurality of independent filters, such as finite impulse response filters, in an efficient manner. Coefficient and data operands associated with each of the independent filters are stored in a predetermined order in a storage device and selectively coupled to an arithmetic unit for processing in a predetermined manner. Calculations for each filter are successively made and selectively stored. Although independent filters exist, processing circuitry is multiplexed and shared to substantially minimize associated control circuitry.