Abstract: Electromechanical resonating devices such as MEMS resonators are provided in semiconductor structures and devices having high-quality monocrystalline semiconductor layers formed by utilizing compliant substrates. The semiconductor layer is patternwise etched to define a vibrational mode resonator member with one or more supports mechanically coupled to the member. A portion beneath the member is etched to provide clearance for vibrational mode operation of the resonating member. The semiconductor layer is selectively doped to define one or more conductive pathways to the resonating member.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. Devices may be formed in the silicon wafer prior to growing the high quality epitaxial layers. Then, to achieve the formation of a compliant substrate, an accommodating buffer layer is grown on silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Compound devices are then formed on the overlying monocrystalline layer.

Abstract: Communication apparatus (100) corrects for amplitude imbalance caused by differences in circuitry that process in-phase and quadrature signals. The in-phase and quadrature signals are alternately routed in rapid succession through first and second parallel processing circuits or signal paths (140, 150) to cancel imbalances between the signal paths. Switches (132, 134) are employed at inputs to and outputs from corresponding portions of both signal paths, and these switches (132, 134) are synchronously operated in response to a control signal to interchange signals on the signal paths.

Abstract: A variable gain control circuit (125, 127) includes a programmable operational transconductance amplifier (OTA) circuit (214) and a programmable conveying circuit (544). The conveying circuit (544) has a programmable differential circuit (550) interconnected to a pair of programming inputs (564, 566). The pair of programming inputs (564, 566) is interconnected to a pair of programming inputs (238, 240) that set the gain of the OTA circuit (214). When the OTA circuit (214) is configured as an operational transconductance filter (112, 113), the programmable differential circuit (550) can adjust the gain of the conveying circuit (544) to compensate for changes in the input impedance of the filter (112, 113). The programming inputs (238, 240) that set the input impedance and bandwidth of the filter (113, 113) also control the amount of signal current transmitted by the conveying circuit (544).

Abstract: A direct current (DC) offset correction loop (200) for determining the required amount of DC offset to an analog input signal includes a digital integrator (211) for measuring the amount of DC offset present at the final output of a forward signal path and a hold circuit (213) for controlling the digital integrator (213). The DC offset correction loop (200) provides a constant amount of DC offset correction to the analog input signal.

Abstract: Second order intermodulation distortion (IM2) occurs when two interfacing signals mix with each other through a second order nonlinearity to produce an intermodulation product at the sum and difference frequencies of the two interferers. To reduce the amount of intermodulation distortion, dynamic matching is employed. In practice, dynamic matching operates to transform coefficients of IM2 distortion from constant values into functions of time where they may be handled by known rejection techniques.

Abstract: A receiver (300) includes input (I.sub.in), output (V.sub.out), forward path with filter (104, and 108), and feedback path with error amplifier (112) coupled into the forward path. Coupled to the feedback path is an error signal storage device (408, 508). A control circuit (320) responsive to input signal amplitude couples to the storage device (408, 508) and retrieves stored error signal information for use by the feedback path. During calibration, a forward path stage is stimulated with a plurality of signals of known amplitude to generate outputs (V.sub.out). The outputs are compared to a reference to generate error signals. Error signal values are stored in memory as a function of input signal amplitude. A plurality of error signal values are stored. During operation, stage input signals are detected and compared with the plurality of signals of known amplitude.

Abstract: A radio (100) has a combined phase locked loop (PLL) (207) and an automatic frequency control (AFC) loop (215, 109, 111) and a method of operating the same. A mixer (201) converts the received RF signal (117) to an intermediate frequency (IF) signal (219) responsive to an injection signal (217). The PLL (207) locks the injection signal (217) to the received RF signal (117) responsive to a difference between the IF signal (219) and a reference signal (119). The AFC loop (215, 109, 111) locks the reference signal (119) to the received RF signal (117) responsive to a difference between the injection signal (217) and the reference signal (119).

Abstract: Receiver section (200) includes a compensation network (202) which compensates for undesired effects caused by synthesized LO (204). Compensation network (202) substantially duplicates the amplitude and phase delay of synthesized LO (204) allowing for a substantially flat demodulated frequency response to be achieved at output (122) which is independent of the bandwidth of synthesized LO (204).

Abstract: A receiver automatic gain control (AGC) circuit includes a first adjustable gain control amplifier (158) which is responsive to a gain control signal (156). The AGC circuit further includes a second adjustable gain control amplifier (114) and a control circuit (116) which receives the gain control signal (156) and provides a modified gain control signal or VCNTRL (152) to the second adjustable control amplifier (114). The control circuit (116) also limits the amount of gain control applied to adjustable gain control amplifiers (114 and 118) when the gain control signal (156) reaches a certain predetermined level. This provides for all further gain reduction to occur at the first adjustable gain control amplifier (158) and thereby reduce the chances for distortion under high input signal conditions.

Abstract: A decoder circuit (21) and method for providing an amplitude compensated signal by removing the undesired effect of amplitude modulation on a phase modulated signal. The decoder method is provided by demodulating a received inphase receive signal component (10) and quadrature receive signal component (12) of the phase modulated signal and outputting an amplitude varying signal (15) to a feedforward automatic gain control circuit that outputs an amplitude compensated signal (38). The feedforward automatic gain control circuit comprises a detector circuit (16), an offset bias circuit (32), a differencer circuit (30) and a gain control circuit (28).The detector circuit (16) outputs a DC signal (17) representing an amplitude of the inphase receive signal (10) and the quadrature receive signal (12). The offset bias circuit (32) provides a constant current bias (29) to the DC signal (17) thus creating a control signal 31.

Abstract: A radio transceiver includes a first local oscillator (114) which is preferably a synthesizer providing a first LO signal, and a second local oscillator providing a second LO signal. The radio further includes a first mixer (110) for mixing the received RF signal and the first LO signal to produce a first IF signal having a frequency which is the difference of the two inputs. The first IF signal is then mixed with the second LO signal by a second mixer (124) where a second IF signal is produced which is preferably at zero frequency. During transmission, the radio uses a conventional modulator to modulate the second LO signal which is then mixed with the first LO signal by a transmitter offset mixer (112), where the output is a modulated RF signal.

Abstract: A wide dynamic range Operational Transconductance Amplifier (OTA) (100) includes a differential voltage to current converter (206) for converting an input voltage to a current level. A pair of programmable folded cascodes (201) are coupled to the output of the converter (206) in order to render the amplifier (100) programmable. Current sources (222 and 226) are employed to provide output sourcing current. There is also included a common mode feedback (106) for maintaining the output signal substantially and equally centered between rails of the operating voltage (208).

Abstract: An electronic circuit (100) includes an output (110) and a filter circuitry (104, 106 and 108) coupled across this forward transmission path is a feedback loop having an error amplifier (112) and a coupling amplifier (116). Switches (118, 120, 122, and 124) are situated around the error amplifier to form an auto zero circuit. A capacitor (114) in conjunction with the error amplifier (112) provides an integrator for the circuit (100). The auto zero circuit allows the output (110) to follow a desired DC voltage namely (VAG) independent of the offset voltage of the error amplifier (112) or the coupler amplifier (116).

Abstract: A digital frequency synthesizer circuit with spur compensation includes a demodulator circuit (118) for demodulating the output signal (116) of the synthesizer's accumulator (108). Demodulator (118) also inverts the signal, and provides an inverted demodulated output signal (142) which is then coupled to the synthesizer clock (124) after passing through a gain stage (122) in order to modulate the synthesizer clock (124) with a compensation signal (146). The compensated clock signal (140) is then sent to accumulator (108) in order to substantially cancel out any jitter in the accumulator's output signal (116). The modulation signal (MOD IN) which is digitally applied to accumulator (108) is applied in analog fashion to the gain stage (122) in order to prevent the desired modulation signal (MOD IN) from being canceled in the output signal (116).

Abstract: A radio transceiver is coupled to a source of a reference waveform, and includes transmit mode receive modes. The transceiver comprises a first down mixer, a first low pass filter coupled the first down mixer, and a first selective coupling switch. The first down mixer is coupled to receive an input signal having an input frequency, for mixing the input signal with the reference waveform to produce a first signal. The first signal has a frequency substantially lower than the input frequency. The first low pass filter is coupled the first down mixer for producing a filtered first signal. The first selective coupling switch couples the first down mixer and the low pass filter when the radio transceiver is in the receive mode, and decouples the first down mixer and the low pass filter when the radio transceiver is in the transmit mode, thus substantially eliminating transient disturbances.

Abstract: An essentially zero intermediate frequency receiver (100) for recovering an information signal from a received signal (110), which includes means for blanking noise signals which may otherwise deteriorate performance, comprises a receiver (10) for recovering the information signal and a noise blanker (28). The receiver (28) comprises at least one conversion mixer (32B) for operating on the received signal (110) to provide an essentially baseband signal (125B), at least one delay filter (40B) coupled to the conversion mixer (32B) for producing a delayed essentially baseband signal, and at least one blanker switch (S1-S4) for operating on the delayed essentially baseband signal to temporarily prevent recovery of the information signal in response to a control signal (58). To provide the control signal (58), the noise blanker (28) is coupled to the receiver (10) for operating on either the essentially baseband signal (125B) or the received signal (110) as a noise blanker input signal.

Abstract: A sideband receiver that locks to a pilot component of a received signal. The pilot component is down-converted and then up-converted prior to phase comparing the pilot component information to provide a lock function. The receiver architecture allows monolithic integration of the receiver on a single integrated circuit (401).

Abstract: An improved frequency synthesizer 100 capable of producing true DC frequency modulation without the need to DC frequency modulate the reference oscillator. The synthesizer 100 includes a phase comparator 104 compares the reference signal 102 and the feedback signal 112. The output of said phase comparator 104 filtered and coupled to the main VCO 108. A balanced image mixer 200 mixes the two signals from the main VCO 108 and an offset VCO 300. The offset VCO 300 is a low frequency (e.g. 100 to 300 KHz) integrated offset VCO 308 whose center frequency is controlled accurately, by means of matching to a VCO 306 which is controlled by a feedback loop, and by using an image balanced mixer 200 to reduce the image response to substantially reduce or eliminate the filtering required at the mixer output. The configuration of the offset mixer within the synthesizer loop, any residual spurious content due to imperfect image balance or carrier feedthrough of the mixer is attenuated by the loop response.

Abstract: In a communication system where outbound communications are comprised of a TDM format, and inbound communications are not, and wherein the outbound communications occasionally include system control information, a method for allowing a transmitting unit to occasionally interrupt its transmissions to allow reception of system control information.