Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

Abstract: Apparatuses and methods for phase interpolators are provided. An example apparatus comprises a phase interpolator and a controller coupled to the phase interpolator. The controller is configured to provide a digital timing code to the phase interpolator, and the phase interpolator is configured to apply a correction to the received digital timing code based, at least in part, on phase interpolator error correction data from a data structure containing phase interpolator error correction data.

Abstract: A method and apparatus for efficiently viewing selected cells using a database editor tool. By using a cell selection list that identifies a number of selected components, the present invention may allow the user to sequentially view the selected components by using a number of pre-defined “hot-keys”. In addition, the present invention may automatically set the design hierarchy in the database editor tool to an appropriate level so that the component being viewed can be easily manipulated by the circuit designer.

Abstract: A method and apparatus for associating selected circuit instances, and for allowing a later group manipulation thereof. Prior to entering a database editor tool, selected instances may be associated with one another, and the association may be recorded in the circuit design database. The database editor tool may then read the circuit design database and identify the selected instances and the association therebetween. The associated instances may be called a group, or preferably a stack. The database editor tool may then perform a group operation on the instances associated with the stack.

Abstract: A placement tool that may import and export cell substitution and/or cell selection lists. The cell substitution and/or cell selection lists may be used by the placement tool to substitute and/or modify the placement design database, rather than the original schematic or behavioral database. This may eliminate the need to re-synthesize the circuit design during each design iteration. The present invention further contemplates providing a reset feature which may reset the circuit design database to a previous state, if desired.

Abstract: A method and apparatus for efficiently selecting cells within a circuit design database. The invention includes four primary features for selecting cells including (1) selecting only those cells that are in a pre-identified region and within a pre-identified selection area; (2) maneuvering through the circuit design hierarchy and selecting cells or regions at selected levels of hierarchy by using predetermined up and down hot-keys; (3) sorting selected cells by instance name, and manually selecting a desired cell or region from the resulting sorted list; and (4) sorting selected cells by a corresponding net name, and manually selecting a desired cell or region from the resulting sorted list.

Abstract: A method and apparatus for selectively viewing nets within a database editor tool. The present invention provides four primary features for selectively viewing nets. First, the present invention contemplates selecting a number of objects, and viewing only those nets that are either driven from or received by the selected objects. In a preferred embodiment, the number of objects are placed objects within a placement tool. Second, for those nets that are selected, and that are also coupled to un-placed cells, the present invention contemplate providing fly-wires from the corresponding selected objects to a predetermined location representative of an approximate expected location for the un-placed cells. Third, the present invention contemplate providing a vector filter which may permit only vectored nets with a selected bus width range to be viewed.

Abstract: A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry which is visible in the virtual address space of the first process. The queue entry is added to a queue by the sending process directing the processor to execute an enqueue instruction. The receiving process removes the queue entry from the queue by directing the processor to execute a dequeue instruction. The receiving process then has direct access and visibility to the contents of the queue entry without having to copy the data into its virtual address space. Instead of sending data in a queue entry, a sending process may send an event indicator and no data.

Abstract: A method and apparatus for distributing clock drivers within a hierarchical circuit design, wherein the clock drivers are concentrated in locations where they are actually needed rather than uniformly distributed throughout the circuit design. In an exemplary embodiment, the actual clock loads within a selected hierarchical region are determined, and a sufficient number of clock drivers are added as children objects to the selected hierarchical region. Since many placement tools may place the children objects within an outer boundary of the corresponding parent object, the clock drivers, as children objects of the selected hierarchical region, may be placed within the outer boundary of the selected hierarchical region. Accordingly, the clock drivers may be concentrated in the locations where actually needed.

Abstract: A method and apparatus for efficiently identifying and resolving conflicts between conflicting cell substitution recommendations. Unlike the prior art, the present invention provides a resolving means within a data processing system to identify and resolve conflicting cell substitution recommendations. The resolving means may categorize the cell substitutions in accordance with a number of predetermined cell substitution types, wherein each of the cell substitution type may be assign a predetermined priority value. Thereafter, the resolving means may identify conflicting cell substitution recommendations, and resolve the conflicts in accordance with the predetermined priority scheme.

Abstract: A method and apparatus for efficiently optimizing a circuit design by substituting identified cells within the circuit design with logically equivalent cells having different drive strengths. The present invention eliminates the need to update the design database and to place and route the circuit design during each design iteration. Rather, an improved extraction tool is provided which incorporates a cell substitution list, and updates the RC file therefrom. The updated RC file is used by the timing analysis tool to determine if the updated design will meet the design specification. After the design meets the design specification, a final place and route may be performed.

Abstract: A method and apparatus for efficiently performing timing analysis on a circuit design. The present invention essentially provides a hybrid between a path enumeration algorithm and a critical path algorithm. As such, the present invention increases the number and degree of timing violations reported by a Critical Path Analysis (CPA) algorithm, while maintaining a performance advantage over a Path Enumeration (PE) algorithm. This is accomplished by providing a number of "pseudo" clocks to selected latches within the circuit design database, thereby tricking the CPA algorithm into reporting more timing violations than would otherwise be reported.

Abstract: A method used by a computer-aided design system for placing logic functions and cells in a floor plan of a very large scale integrated circuit chip. The structure of a set of selected logic functions and cells to be placed is compared to a set of selected logic functions and cells which have previously been placed in the floor plan. If the number of cells and the structure of the sets are analogous, the selected logic functions and cells to be placed are automatically assigned physical positions in the floor plan based on the physical position and structure of the selected logic functions and cells that have already been placed, and on an orientation mode. The orientation mode provides for the reflection of the placement of the selected logic functions and cells about the horizontal axis, the vertical axis, or both the horizontal and vertical axes.

Abstract: A base address prediction system for predicting one of a plurality of base addresses to be added to a known relative address in order to generate an absolute address. An actual base address determined from the relative address is also generated. The actual base address determination takes longer to generate than the predicted base address determination, and therefore the predicted base address is used to select a base address as long as the prediction is correct. Circuitry exists to compare the predicted base address with the actual base address, and if not equal, the predicted base address will be nullified, and the actual base address will be used. Prediction modes are dependent on whether the relative address indicates an instruction fetch or an operand fetch. Where the relative address indicates an instruction fetch, the prediction will be based on the last base address used, on the assumption that instructions will be contiguous in a single block of memory.

Abstract: A digital instruction processor control system for an instruction processor having a multiple stage instruction execution pipeline capable of executing binary instructions in fixed predetermined stages. The control system includes a hardware controller to generate control signals for execution of all pipeline stages of standard instructions and for the first stage of extended cycle instructions and provides a main microcode controller to provide programmed control signals for controlling all subsequent stages of execution of extended cycle instructions. The control system also utilizes a separate sequence microcode controller for execution of certain instructions of a predetermined type including decimal instruction execution, during which time the main microcode controller is under control of the separate sequence controller.

Abstract: A system and method for interprocess communication between concurrently executing, cooperating sequential processes in a digital computer system uses a shared memory queue as a mechanism for message passing and process synchronization. Data to be transferred from a sending process to a receiving process is stored in a queue entry on the shared memory queue. Hierarchical queuing allows a sending process to collect multiple message segments as entries in a local sub-queue, which is enqueued as a single entity to the shared memory queue when all message segments are present. The receiving process dequeues the sub-queue in one operation, thereby increasing the efficiency of message transfer while preventing the erroneous dequeuing of message segments when multiple receiving processes are waiting on the same shared memory queue. In this manner, the logical maximum size of a message being passed between processes is expanded.