Abstract: A calibration circuit for a pulse generator which produces pulse rise and pulse fall times by charging and discharging a capacitor at selected currents and clamps the pulse high voltage output and pulse low voltage output at selectable voltage levels. An output voltage error is developed by comparing each output voltage to a reference clamping voltage. The output voltage error is converted to digital form for storage and then reconverted back into a voltage where it effectively compensates the reference clamping voltage, thereby removing the error from the output voltage. The pulse generator output can be calibrated for any combination of currents and voltages and also for any amplification factor selected for the output amplifier.

Abstract: A frequency synthesizer is disclosed having n identical digital module stages, each of which stages generates one digit of the final frequency number of the synthesized frequency output signal. Each digit module stage comprises a series arrangement of a phase lock loop, a digit adder, and a digit shifter. The present invention provides a synthesized frequency generator with components that are inexpensive and readily available commercially, and moreover the frequency synthesizer is digitally controllable such that it is compatible with other digital control circuits.

Abstract: The digital test probe has an electrically conductive probe needle for making electrical contact with different test locations of a digital circuit. A logic level detector connected to the needle provides a data signal having a logic level representative of that at the test location. N indicators, such as light emitting diodes, are provided with each presenting an indication of the logic level at an associated one of N test location. A memory has N storage locations and each stores a binary level signal representative of the logic level at an associated one of N test locations. Each time the operator actuates a switch, data representing the logic level at that test location is written into an associated location in the memory. In this way, the operator need not divert his attention from the probing of test locations to look at the indicators while testing the various locations since the indicators will provide him with a visual readout after he has finished.

Abstract: A noise insensitive comparator is disclosed which includes an output circuit, such as a bistable flip-flop, which is triggerable to provide an indication and an output control circuit which responds to the first and second signals which are to be compared for triggering the output circuit in accordance therewith. The output control circuit triggers the output circuit to provide the indication when the values of the first and second signals cross over, but only if the first and second signal values have deviated from one another by more than a selected amount since the output circuit was last triggered. This prevents erroneous retriggering of the output circuit due to noise in the first and second signals.