Abstract: A digital-to-synchro converter is provided where a binary input code specifies a desired shaft angle and where an resolver type position transducer is employed with additional circuitry to generate a shaft position error signal indicative of the angular difference between the desired shaft angle and the actual shaft angle. The additional circuitry corrects for known and calculated errors in the shaft position detection process and equipment.

Abstract: A phase/frequency detector to detect the phase/frequency difference between two signals comprises a first bistable circuit to produce a first output pulse in response to one of the two signals; a second bistable circuit to produce a second output pulse in response to the other of the two signals; a gate circuit coupled to the first and second bistable circuits responsive to the first and second output pulses to produce a reset pulse to reset the first and second bistable circuits after a predetermined time delay. A first circuit arrangement is coupled to the first bistable circuit and the gate circuit to reduce the width of the first output pulse and a second circuit arrangement is coupled to the second bistable circuit and the gate circuit to reduce the width of and invert the second output pulse. The second circuit arrangement includes a third circuit arrangement to equalize turn on and turn off times of the reduced width first output pulse and the reduced width second output pulse.

Abstract: Apparatus is provided for generating a recovered clock signal having pulses with a selected transitory edge timed to occur at the center of the eye intervals of a multilevel digital signal.

Abstract: A precision quadrature analog phase detector provides a controllable amount of amplification of a signal that is then applied to a double balanced mixer for comparison with a reference signal. Outputs of the mixer are attenuated an amount equal in proportion to the amount of amplification to provide a constant overall gain. The double balanced mixer thus receives signals at a relatively high and substantially constant level regardless of the level of the input. Means are also provided for controlling offset.