Patents by Inventor Joseph P. Ramon

Joseph P. Ramon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer having scribe line test modules including matching portions from subcircuits on active die
    Patent number: 8134382
    Abstract: A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: March 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Tathagata Chatterjee, Joseph P. Ramon, Patricia Vincent
  • SEMICONDUCTOR WAFER HAVING SCRIBE LINE TEST MODULES INCLUDING MATCHING PORTIONS FROM SUBCIRCUITS ON ACTIVE DIE
    Publication number: 20110253999
    Abstract: A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension.
    Type: Application
    Filed: April 15, 2010
    Publication date: October 20, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata Chatterjee, Joseph P. Ramon, Patricia D. Vincent