Abstract: This application discloses a supply chain security technique that enrolls an integrated circuit with a security server and subsequently utilizes the enrollment to authenticate the integrated circuit. The integrated circuit can include security circuitry to enroll the integrated circuit with the security server by generating an enrollment message—including a fingerprint code having an encoded version of a private value generated by the security circuitry—for transmission to the security server. The security circuitry can authenticate the integrated circuit by replying to a request to verify authentication of the integrated circuit from the security server. The response can confirm to the security server that the integrated circuit includes the private value, which can authenticate the integrated circuit.

Abstract: This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can utilize transforms to derive bits from the outputs and utilize the derived bits to generate an identifier for the physical unclonable function device. An inspection configuration tool can sample multiple outputs from each of the physical unclonable function units, identify a transforms to perform on a future output for each of the physical unclonable function units based on a distribution of values corresponding to the sampled outputs. The inspection configuration tool can configure the physical unclonable function device to perform the transforms on the future outputs of the physical unclonable function units. Embodiments will be described below in greater detail.

Abstract: This application discloses an electronic system including active circuitry configured to be selectively enabled for authorized number of times. The electronic system also includes security circuitry to detect an enablement event associated with the electronic system. The enablement event can correspond to reception of a reset signal associated with the electronic system, a lapse of a predetermined time period, or the like. In response to the detection of the enablement event, the security circuitry can determine a number of times the security circuitry has previously enabled the active circuitry. The security circuitry can generate the enablement signals capable of enabling the active circuitry when the determined number of times the security circuitry has previously enabled the active circuitry is fewer than the authorized number of times.

Abstract: This application discloses an electronic system including active circuitry configured to be selectively enabled for authorized number of times. The electronic system also includes security circuitry to detect an enablement event associated with the electronic system. The enablement event can correspond to reception of a reset signal associated with the electronic system, a lapse of a predetermined time period, or the like. In response to the detection of the enablement event, the security circuitry can determine a number of times the security circuitry has previously enabled the active circuitry. The security circuitry can generate the enablement signals capable of enabling the active circuitry when the determined number of times the security circuitry has previously enabled the active circuitry is fewer than the authorized number of times.

Abstract: This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can extract bits from the outputs at various inspection locations and utilize the extracted bits to generate an identifier for the physical unclonable function device. An inspection configuration tool can identify the inspection locations and configure the physical unclonable function device with the inspection locations. The inspection configuration tool can sample the physical unclonable function circuitry to identify a plurality of multi-bit outputs, select bit locations in the multi-bit outputs as inspection locations based on bit value stability for the bit locations, and configure the identifier generation circuitry in physical unclonable function device with the inspection locations.

Abstract: This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can utilize transforms to derive bits from the outputs and utilize the derived bits to generate an identifier for the physical unclonable function device. An inspection configuration tool can sample multiple outputs from each of the physical unclonable function units, identify a transforms to perform on a future output for each of the physical unclonable function units based on a distribution of values corresponding to the sampled outputs. The inspection configuration tool can configure the physical unclonable function device to perform the transforms on the future outputs of the physical unclonable function units. Embodiments will be described below in greater detail.

Abstract: This application discloses a supply chain security technique that enrolls an integrated circuit with a security server and subsequently utilizes the enrollment to authenticate the integrated circuit. The integrated circuit can include security circuitry to enroll the integrated circuit with the security server by generating an enrollment message—including a fingerprint code having an encoded version of a private value generated by the security circuitry—for transmission to the security server. The security circuitry can authenticate the integrated circuit by replying to a request to verify authentication of the integrated circuit from the security server. The response can confirm to the security server that the integrated circuit includes the private value, which can authenticate the integrated circuit.

Abstract: A method and system for routing signals through interconnect matrices in a programmable logic device such that downstream routing failures can be reduced. In one embodiment, the invention is used to improve routing in complex programmable logic devices or CPLDs, however, the invention can be applied to other programmable devices and routing resources. In routing a set of signals through an upstream interconnect matrix or PIM, the method determines a set of high priority signals. In routing the upstream PIM, the method uses a Maximum Bipartite Matching process in one embodiment to route the original signals once. The duplicated high priority signals are then routed and sent to the input array of the downstream interconnect matrix along with the originally routed signals. From the originally routed signals and the duplicate signals, the downstream interconnect matrix routes each unique signal once and only once depending on the available routing resources.