Patents by Inventor Joseph R. Abel
Joseph R. Abel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250230546Abstract: Various embodiments herein relate to apparatuses, systems, and methods for selective control of multi-station processing chamber components. In some embodiments, a method comprises: determining for a station of a plurality of stations, a number of deposition cycles to be performed; causing a first number of deposition cycles to be performed for each of the plurality of stations by causing a first plurality of control components associated with a first station and a second plurality of control components associated with a second station to be set to a first position; and responsive to determining that the first number of deposition cycles has been completed: causing at least one component of the first plurality of control components to be changed to a second position; and causing additional deposition cycles to be performed for the second station by causing the second plurality of control components to remain in the first position.Type: ApplicationFiled: September 22, 2022Publication date: July 17, 2025Inventors: Douglas Walter Agnew, Eli Jeon, Daniel Boatright, Trung T. Le, Tuan Anh Nguyen, Cody Barnett, Joseph R. Abel, Siddappa Attur, Mani Sankaran Kartha
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Publication number: 20250179632Abstract: Atomic layer deposition (ALD) of dielectric material in gaps that facilitates void-free bottom-up gap fill can involve flowing a reaction inhibitor during the ALD process. In some embodiments, the reaction inhibitor is flowed during at least part of a plasma operation of a plasma-enhanced ALD (PEALD) process.Type: ApplicationFiled: February 28, 2023Publication date: June 5, 2025Inventors: Tao ZHANG, Pulkit AGARWAL, Joseph R. ABEL, Shiva Sharan BHANDARI, Jennifer Leigh PETRAGLIA
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Patent number: 12322619Abstract: Methods and system are provided for dynamic process control in substrate processing, for example in semiconductor manufacturing applications. Some example systems and methods are provided for advanced monitoring and machine learning in atomic layer deposition (ALD) processes. Some examples also relate to dynamic process control and monitoring for chamber parameter matching and gas line charge times.Type: GrantFiled: August 11, 2020Date of Patent: June 3, 2025Assignee: Lam Research CorporationInventors: Purushottam Kumar, Tengfei Miao, Gengwei Jiang, Daniel Ho, Joseph R. Abel, Siddappa Attur, Pulkit Agarwal
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Publication number: 20250154644Abstract: Methods of filling a gap with a dielectric material including using an inhibition plasma during deposition. The inhibition plasma increases a nucleation barrier of the deposited film. The inhibition plasma selectively interacts near the top of the feature, inhibiting deposition at the top of the feature compared to the bottom of the feature, enhancing bottom-up fill. A process chamber may have multiple pressure switches to enable a process after deposition at a higher pressure than the pressure during deposition.Type: ApplicationFiled: February 14, 2023Publication date: May 15, 2025Inventors: Eli Jeon, Douglas Walter Agnew, Shiva Sharan Bhandari, Ian John Curtin, Joseph R. Abel, Jason Alexander Varnell, Cody Barnett, Christopher Nicholas Iadanza, Dustin Zachary Austin
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Patent number: 12288685Abstract: Methods and apparatuses for modifying a wafer surface using an organosilicon precursor are provided herein. The wafer surface is dosed with the organosilicon precursor following deposition of a dielectric material by an atomic layer deposition (ALD) process. In some implementations, the dielectric layer is made of silicon oxide. Dosing the wafer surface with the organosilicon precursor may occur in the same chamber as the ALD process. The organosilicon precursor may modify the wafer surface to increase its hydrophobicity so that photoresist adhesion is improved on the wafer surface. In some implementations, the wafer surface may be exposed to an inert gas RF plasma after dosing the wafer surface with the organosilicon precursor.Type: GrantFiled: April 8, 2019Date of Patent: April 29, 2025Assignee: Lam Research CorporationInventors: Jeremy D. Fields, Awnish Gupta, Douglas W. Agnew, Joseph R. Abel, Purushottam Kumar
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Patent number: 12252782Abstract: Methods for filling gaps with dielectric material involve deposition using an atomic layer deposition (ALD) technique to fill a gap followed by deposition of a cap layer on the filled gap by a chemical vapor deposition (CVD) technique. The ALD deposition may be a plasma-enhanced ALD (PEALD) or thermal ALD (tALD) deposition. The CVD deposition may be plasma-enhanced CVD (PECVD) or thermal CVD (tCVD) deposition. In some embodiments, the CVD deposition is performed in the same chamber as the ALD deposition without intervening process operations. This in-situ deposition of the cap layer results in a high throughput process with high uniformity. After the process, the wafer is ready for chemical-mechanical planarization (CMP) in some embodiments.Type: GrantFiled: December 1, 2020Date of Patent: March 18, 2025Assignee: Lam Research CorporationInventors: Jeremy David Fields, Ian John Curtin, Joseph R. Abel, Frank Loren Pasquale, Douglas Walter Agnew
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Publication number: 20250062118Abstract: Methods of filling a gap with a dielectric material including using an inhibitor plasma during deposition. When the inhibitor plasma interacts with material in the feature, the material at the bottom of the feature receives less plasma treatment than material located closer to a top portion of the feature or in field. Deposition at the top of the feature is then selectively inhibited and deposition in lower portions of the feature proceeds with less inhibition or without being inhibited. As a result, bottom-up fill is enhanced, which can create a sloped profile that mitigates the seam effect and prevents void formation. In some embodiments, the inhibitor plasma is used at a higher pressure to increase the rate of inhibition, improving throughput.Type: ApplicationFiled: December 14, 2022Publication date: February 20, 2025Inventors: Dustin Zachary Austin, Joseph R. Abel, Aaron R. Fellis, Douglas Walter Agnew, Bart J. Van Schravendijk
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Publication number: 20250054752Abstract: Methods of filling a gap with a dielectric material including using an inhibition plasma during deposition. The inhibition plasma increases a nucleation barrier of the deposited film. The inhibition plasma selectively interacts near the top of the feature, inhibiting deposition at the top of the feature compared to the bottom of the feature, enhancing bottom-up fill. The inhibition plasma may also be used to etch portions of the feature to reduce void formation.Type: ApplicationFiled: December 15, 2022Publication date: February 13, 2025Inventors: Dustin Zachary Austin, Joseph R. Abel
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Publication number: 20250046613Abstract: A method for doping a substrate is provided. A silicon oxide diffusion barrier layer is formed on a surface of the substrate. At least one dopant layer is deposited over the silicon oxide diffusion barrier layer. A cap layer is deposited over the at least one dopant layer forming a stack of the substrate, the silicon oxide diffusion layer, the at least one dopant layer, and the cap layer. The stack is annealed. The cap layer, at least one dopant layer, and the silicon oxide diffusion barrier layer are removed.Type: ApplicationFiled: October 21, 2024Publication date: February 6, 2025Inventors: Purushottam KUMAR, Gengwei JIANG, Bart J. VAN SCHRAVENDIJK, Tengfei MIAO, Joseph R. ABEL, Adrien LAVOIE
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Patent number: 12125705Abstract: A method for doping a substrate is provided. A silicon oxide diffusion barrier layer is formed on a surface of the substrate. At least one dopant layer is deposited over the silicon oxide diffusion barrier layer. A cap layer is deposited over the at least one dopant layer forming a stack of the substrate, the silicon oxide diffusion layer, the at least one dopant layer, and the cap layer. The stack is annealed. The cap layer, at least one dopant layer, and the silicon oxide diffusion barrier layer are removed.Type: GrantFiled: March 17, 2020Date of Patent: October 22, 2024Assignee: LAM RESEARCH CORPORATIONInventors: Purushottam Kumar, Gengwei Jiang, Bart J. Van Schravendijk, Tengfei Miao, Joseph R. Abel, Adrien Lavoie
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Publication number: 20240347337Abstract: Various embodiments include methods to produce low dielectric-constant (low-?) films. In one embodiment, alternating ALD cycles and dopant materials are used to generate a new family of silicon low-? materials. Specifically, these materials were developed to fill high-aspect-ratio structures with re-entrant features. However, such films are also useful in blanket applications where conformal nanolaminates are applicable. Various embodiments also disclose SiOF as well as SiOCF, SiONF, GeOCF, and GeOF. Analogous films may include halide derivatives with iodine and bromine (e.g., replace “F” with “I” or “Br”). Other methods, chemistries, and techniques are disclosed.Type: ApplicationFiled: May 6, 2024Publication date: October 17, 2024Inventors: Joseph R. Abel, Douglas Walter Agnew, Adrien Lavoie, Ian John Curtin, Purushottam Kumar
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Publication number: 20240327973Abstract: A method comprising: providing a substrate in a processing station comprising a substrate support and a showerhead, the substrate comprising a gap to be filled; and depositing silicon-containing film in the gap by a plasma-enhanced atomic layer deposition (PEALD) process comprising multiple cycles of operations (a)-(d): (a) a dose operation comprising flowing a silicon-containing precursor into the processing station via the showerhead to allow the silicon-containing precursor to adsorb onto the substrate; (b) after (a), flowing a purge gas into the processing station; (c) after (b), exposing the substrate to plasma species to react with the adsorbed silicon-containing precursor; and (d) after (c), flowing a purge gas into the processing station, wherein the silicon-containing precursor continues to flow into the processing station during at least (b).Type: ApplicationFiled: July 1, 2022Publication date: October 3, 2024Inventors: Ravi KUMAR, Pulkit AGARWAL, Adrien LAVOIE, Dustin Zachary AUSTIN, Joseph R. ABEL, Douglas Walter AGNEW, Jonathan Grant BAKER
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Patent number: 12087574Abstract: A method for processing a substrate is described. A first reactant in vapor phase is introduced into a reaction chamber having the substrate therein. The first reactant is allowed to be adsorb onto the substrate surface. The non-reactive portion of the first reactant is purged from the reaction chamber after a flow of the first reactant has ceased. The second reactant is introduced in vapor phase into the reaction chamber while the first reactant is adsorbed onto the substrate surface. The second reactant comprises a 1:1:1 ratio of dihydrogen (H2), a nitro-gen-containing reactant, and an oxygen-containing reactant. A plasma is ignited based on the second reactant. The substrate surface is exposed to the plasma. The plasma is extinguished. Gas from the reaction chamber is purged.Type: GrantFiled: June 27, 2019Date of Patent: September 10, 2024Assignee: Lam Research CorporationInventors: Douglas Walter Agnew, Joseph R. Abel, Bart Jan van Schravendijk
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Publication number: 20240222151Abstract: The present disclosure relates to a system for a semiconductor processing. The system includes a semiconductor processing chamber having a plurality of processing stations, a plurality of manifold trunks, a plurality of valves, and a plurality of fluid manifolds. Each manifold trunk includes an outlet, a common flowpath, a plurality of trunk inlets, a plurality of orifices, and a plurality of valve interfaces.Type: ApplicationFiled: April 28, 2022Publication date: July 4, 2024Inventors: Eli Jeon, Michael Philip Roberts, Douglas Walter Agnew, Daniel Boatright, Arun Anandhan Duraisamy, Joseph R. Abel, William Laurence McDaniel
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Patent number: 12020923Abstract: Various embodiments include methods to produce low dielectric-constant (low-k) films. In one embodiment, alternating ALD cycles and dopant materials are used to generate a new family of silicon low-k materials. Specifically, these materials were developed to fill high-aspect-ratio structures with re-entrant features. However, such films are also useful in blanket applications where conformal nanolaminates are applicable. Various embodiments also disclose SiOF as well as SiOCF, SiONF, GeOCF, and GeOF. Analogous films may include halide derivatives with iodine and bromine (e.g., replace “F” with “I” or “Br”). Other methods, chemistries, and techniques are disclosed.Type: GrantFiled: September 20, 2019Date of Patent: June 25, 2024Assignee: Lam Research CorporationInventors: Joseph R. Abel, Douglas Walter Agnew, Adrien Lavoie, Ian John Curtin, Purushottam Kumar
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Publication number: 20240167153Abstract: In one example, a method for depositing a film on a substrate comprises arranging a substrate on a substrate support in a processing chamber and setting a processing pressure, temperature and pressure in the chamber. The method includes striking a plasma and depositing and annealing the film on the substrate at a thickness in a predetermined film thickness range.Type: ApplicationFiled: March 25, 2022Publication date: May 23, 2024Inventors: Awnish Gupta, Douglas Walter Agnew, Bart Jan van Schravendijk, Joseph R. Abel, Frank L. Pasquale, Adrien Lavoie
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Publication number: 20230317449Abstract: Various embodiments herein relate to methods and apparatus for depositing doped and undoped silicon-containing films having a high degree of purity. In one example, the method includes exposing the substrate to a first reactant and a second reactant; reacting the first and second reactants with one another to form a silicon-containing material and depositing a portion of the silicon-containing film on the substrate; before the silicon-containing film is complete, performing an impurity reduction operation including: (i) generating a plasma from a plasma generation gas comprising inert gas and hydrogen, where the plasma generation gas is substantially free of oxygen, and (ii) exposing the substrate to the plasma to thereby reduce a concentration of fluorine, carbon, hydrogen, and/or nitrogen in the silicon-containing film; and repeating these operations (or a subset thereof) until the silicon-containing film is deposited to a final thickness.Type: ApplicationFiled: July 27, 2021Publication date: October 5, 2023Inventors: Awnish Gupta, Bart J. Van Schravendijk, Jason Alexander Varnell, Joseph R. Abel, Jennifer Leigh Petraglia, Adrien LaVoie
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Publication number: 20230307290Abstract: Methods of forming air gaps in hole and trench structures are disclosed. The methods may be used to form buried voids, i.e., voids for which the top is below the top of the adjacent features. The methods include inhibition of the hole or trench structures and selective deposition at the top of the structure forming an air gap within the structures. In some embodiments, the methods are to reduce intra-level capacitance in semiconductor devices.Type: ApplicationFiled: June 28, 2021Publication date: September 28, 2023Inventors: Joseph R. ABEL, Bart J. VAN SCHRAVENDIJK, Ian John CURTIN, Douglas Walter AGNEW, Dustin Zachary AUSTIN, Awnish GUPTA
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Publication number: 20230245896Abstract: Methods and apparatuses for depositing dielectric films into features on semiconductor substrates are described herein. Methods involve depositing dielectric films by using controlled thermal chemical vapor deposition, with periodic passivation operations and densification to modulate film properties.Type: ApplicationFiled: July 21, 2021Publication date: August 3, 2023Inventors: Awnish Gupta, Bart J. Van Schravendijk, Frank Loren Pasquale, Adrien LaVoie, Jason Alexander Varnell, Praneeth Ramasagaram, Joseph R. Abel, Jennifer Leigh Petraglia, Dustin Zachary Austin
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Publication number: 20230175117Abstract: Methods of filling a gap with a dielectric material including using an inhibitor plasma during deposition. The inhibitor plasma increases a nucleation barrier of the deposited film. When the inhibitor plasma interacts with material in the feature, the material at the bottom of the feature receives less plasma treatment than material located closer to a top portion of the feature or in field. Deposition at the top of the feature is then selectively inhibited and deposition in lower portions of the feature proceeds with less inhibition or without being inhibited. As a result, bottom-up fill is enhanced, which can create a sloped profile that mitigates the seam effect and prevents void formation. In some embodiments, an underlying material at the top of the feature is protected using an integrated liner. In some embodiments, a hydrogen chemistry is used during gap fill to reduce seam formation.Type: ApplicationFiled: March 31, 2021Publication date: June 8, 2023Inventors: Dustin Zachary AUSTIN, Ian John CURTIN, Joseph R. ABEL, Bart J. VAN SCHRAVENDIJK, Seshasayee VARADARAJAN, Adrien LAVOIE, Jeremy David FIELDS, Pulkit AGARWAL, Shiva Sharan BHANDARI