Abstract: Methods of filling a gap with a dielectric material including using an inhibitor plasma during deposition. When the inhibitor plasma interacts with material in the feature, the material at the bottom of the feature receives less plasma treatment than material located closer to a top portion of the feature or in field. Deposition at the top of the feature is then selectively inhibited and deposition in lower portions of the feature proceeds with less inhibition or without being inhibited. As a result, bottom-up fill is enhanced, which can create a sloped profile that mitigates the seam effect and prevents void formation. In some embodiments, the inhibitor plasma is used at a higher pressure to increase the rate of inhibition, improving throughput.

Abstract: Methods of filling a gap with a dielectric material including using an inhibition plasma during deposition. The inhibition plasma increases a nucleation barrier of the deposited film. The inhibition plasma selectively interacts near the top of the feature, inhibiting deposition at the top of the feature compared to the bottom of the feature, enhancing bottom-up fill. The inhibition plasma may also be used to etch portions of the feature to reduce void formation.

Abstract: A method for doping a substrate is provided. A silicon oxide diffusion barrier layer is formed on a surface of the substrate. At least one dopant layer is deposited over the silicon oxide diffusion barrier layer. A cap layer is deposited over the at least one dopant layer forming a stack of the substrate, the silicon oxide diffusion layer, the at least one dopant layer, and the cap layer. The stack is annealed. The cap layer, at least one dopant layer, and the silicon oxide diffusion barrier layer are removed.

Abstract: A method for doping a substrate is provided. A silicon oxide diffusion barrier layer is formed on a surface of the substrate. At least one dopant layer is deposited over the silicon oxide diffusion barrier layer. A cap layer is deposited over the at least one dopant layer forming a stack of the substrate, the silicon oxide diffusion layer, the at least one dopant layer, and the cap layer. The stack is annealed. The cap layer, at least one dopant layer, and the silicon oxide diffusion barrier layer are removed.

Abstract: Various embodiments include methods to produce low dielectric-constant (low-?) films. In one embodiment, alternating ALD cycles and dopant materials are used to generate a new family of silicon low-? materials. Specifically, these materials were developed to fill high-aspect-ratio structures with re-entrant features. However, such films are also useful in blanket applications where conformal nanolaminates are applicable. Various embodiments also disclose SiOF as well as SiOCF, SiONF, GeOCF, and GeOF. Analogous films may include halide derivatives with iodine and bromine (e.g., replace “F” with “I” or “Br”). Other methods, chemistries, and techniques are disclosed.

Abstract: A method comprising: providing a substrate in a processing station comprising a substrate support and a showerhead, the substrate comprising a gap to be filled; and depositing silicon-containing film in the gap by a plasma-enhanced atomic layer deposition (PEALD) process comprising multiple cycles of operations (a)-(d): (a) a dose operation comprising flowing a silicon-containing precursor into the processing station via the showerhead to allow the silicon-containing precursor to adsorb onto the substrate; (b) after (a), flowing a purge gas into the processing station; (c) after (b), exposing the substrate to plasma species to react with the adsorbed silicon-containing precursor; and (d) after (c), flowing a purge gas into the processing station, wherein the silicon-containing precursor continues to flow into the processing station during at least (b).

Abstract: A method for processing a substrate is described. A first reactant in vapor phase is introduced into a reaction chamber having the substrate therein. The first reactant is allowed to be adsorb onto the substrate surface. The non-reactive portion of the first reactant is purged from the reaction chamber after a flow of the first reactant has ceased. The second reactant is introduced in vapor phase into the reaction chamber while the first reactant is adsorbed onto the substrate surface. The second reactant comprises a 1:1:1 ratio of dihydrogen (H2), a nitro-gen-containing reactant, and an oxygen-containing reactant. A plasma is ignited based on the second reactant. The substrate surface is exposed to the plasma. The plasma is extinguished. Gas from the reaction chamber is purged.

Abstract: The present disclosure relates to a system for a semiconductor processing. The system includes a semiconductor processing chamber having a plurality of processing stations, a plurality of manifold trunks, a plurality of valves, and a plurality of fluid manifolds. Each manifold trunk includes an outlet, a common flowpath, a plurality of trunk inlets, a plurality of orifices, and a plurality of valve interfaces.

Abstract: Various embodiments include methods to produce low dielectric-constant (low-k) films. In one embodiment, alternating ALD cycles and dopant materials are used to generate a new family of silicon low-k materials. Specifically, these materials were developed to fill high-aspect-ratio structures with re-entrant features. However, such films are also useful in blanket applications where conformal nanolaminates are applicable. Various embodiments also disclose SiOF as well as SiOCF, SiONF, GeOCF, and GeOF. Analogous films may include halide derivatives with iodine and bromine (e.g., replace “F” with “I” or “Br”). Other methods, chemistries, and techniques are disclosed.

Abstract: In one example, a method for depositing a film on a substrate comprises arranging a substrate on a substrate support in a processing chamber and setting a processing pressure, temperature and pressure in the chamber. The method includes striking a plasma and depositing and annealing the film on the substrate at a thickness in a predetermined film thickness range.

Abstract: Various embodiments herein relate to methods and apparatus for depositing doped and undoped silicon-containing films having a high degree of purity. In one example, the method includes exposing the substrate to a first reactant and a second reactant; reacting the first and second reactants with one another to form a silicon-containing material and depositing a portion of the silicon-containing film on the substrate; before the silicon-containing film is complete, performing an impurity reduction operation including: (i) generating a plasma from a plasma generation gas comprising inert gas and hydrogen, where the plasma generation gas is substantially free of oxygen, and (ii) exposing the substrate to the plasma to thereby reduce a concentration of fluorine, carbon, hydrogen, and/or nitrogen in the silicon-containing film; and repeating these operations (or a subset thereof) until the silicon-containing film is deposited to a final thickness.

Abstract: Methods of forming air gaps in hole and trench structures are disclosed. The methods may be used to form buried voids, i.e., voids for which the top is below the top of the adjacent features. The methods include inhibition of the hole or trench structures and selective deposition at the top of the structure forming an air gap within the structures. In some embodiments, the methods are to reduce intra-level capacitance in semiconductor devices.

Abstract: Methods and apparatuses for depositing dielectric films into features on semiconductor substrates are described herein. Methods involve depositing dielectric films by using controlled thermal chemical vapor deposition, with periodic passivation operations and densification to modulate film properties.

Abstract: Methods of filling a gap with a dielectric material including using an inhibitor plasma during deposition. The inhibitor plasma increases a nucleation barrier of the deposited film. When the inhibitor plasma interacts with material in the feature, the material at the bottom of the feature receives less plasma treatment than material located closer to a top portion of the feature or in field. Deposition at the top of the feature is then selectively inhibited and deposition in lower portions of the feature proceeds with less inhibition or without being inhibited. As a result, bottom-up fill is enhanced, which can create a sloped profile that mitigates the seam effect and prevents void formation. In some embodiments, an underlying material at the top of the feature is protected using an integrated liner. In some embodiments, a hydrogen chemistry is used during gap fill to reduce seam formation.

Abstract: Methods of depositing silicon oxide on carbon-based films on a substrate involve adsorbing a silicon-containing reactant on the substrate surfaces, generating oxygen radicals from N2O, and exposing the adsorbed silicon-containing reactant to the oxygen radicals to form a silicon oxide film. In some embodiments, the carbon-based films form features having sidewalls. The methods result in low carbon loss and substantially vertical sidewalls. Embodiments of the methods are performed at high temperatures that facilitate high quality deposition.

Abstract: A method for forming features over a wafer with a carbon based deposition is provided. The carbon based deposition is pretuned, wherein the pretuning causes a non-uniform removal of some of the carbon based deposition. An oxide deposition is deposited through an atomic layer deposition process, wherein the depositing the oxide deposition causes a non-uniform removal of some of the carbon based deposition. At least one additional process is provided, wherein the at least one additional process completes formation of features over the wafer, wherein the features are more uniform than features that would be formed without pretuning.

Abstract: A NAND structure and method of fabricating the structure are described. A multi-layer ONON stack is deposited on a Si substrate and a field oxide grown thereon. A portion of the field oxide is removed, and high-aspect-ratio channels are etched in the stack. The channels are filled with a Si oxide using a thermal ALD process. The thermal ALD process includes multiple growth cycles followed by a passivation cycle. Each growth cycle includes treating the surface oxide surface using an inhibitor followed by multiple cycles to deposit the oxide on the treated surface using a precursor and source of the oxide. The passivation after the growth cycle removes the residual inhibitor. The Si oxide is recess etched using a wet chemical etch of DHF and then capped using a poly-Si cap.

Abstract: Methods for filling gaps with dielectric material involve deposition using an atomic layer deposition (ALD) technique to fill a gap followed by deposition of a cap layer on the filled gap by a chemical vapor deposition (CVD) technique. The ALD deposition may be a plasma-enhanced ALD (PEALD) or thermal ALD (tALD) deposition. The CVD deposition may be plasma-enhanced CVD (PECVD) or thermal CVD (tCVD) deposition. In some embodiments, the CVD deposition is performed in the same chamber as the ALD deposition without intervening process operations. This in-situ deposition of the cap layer results in a high throughput process with high uniformity. After the process, the wafer is ready for chemical-mechanical planarization (CMP) in some embodiments.

Abstract: Methods and apparatuses for depositing material into high aspect ratio features are described herein. Methods involve depositing an oxide material using a hydrogen-containing oxidizing chemistry. Methods may also involve thermally treating deposited oxide material in the presence of hydrogen to remove seams within the deposited oxide material.

Abstract: Methods and system are provided for dynamic process control in substrate processing, for example in semiconductor manufacturing applications. Some example systems and methods are provided for advanced monitoring and machine learning in atomic layer deposition (ALD) processes. Some examples also relate to dynamic process control and monitoring for chamber parameter matching and gas line charge times.