Patents by Inventor Joseph R. Gigante

Joseph R. Gigante has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4532702
    Abstract: A method of fabrication of an electrical connection between two vertically spaced conducting layers in an integrated circuit structure. The first conducting layer is a selected area of the semiconductive substrate which is otherwise covered with a dielectric layer. The exposed selected area of the semiconductive substrate is treated with an activation agent and a selected conductor is chemically vapor deposited upon the activated selected area of the semiconductive substrate. The selected conductor interconnect is built up in successive chemical vapor deposition steps preceded by activation treatment of the exposed top surface until the conductor interconnect is approximately equal to the thickness of the dielectric layer and has a highly planar surface upon which can be readily deposited the second conductive layer which is thus interconnected to the semiconductor substrate.
    Type: Grant
    Filed: November 4, 1983
    Date of Patent: August 6, 1985
    Assignee: Westinghouse Electric Corp.
    Inventors: Joseph R. Gigante, Rathindra N. Ghoshtagore
  • Patent number: 4522657
    Abstract: Disclosed is a low temperature technique for annealing implantation damage and activating dopants. Conventional furnace annealing requires temperatures as high as 1000.degree. to 1100.degree. C. to completely anneal the dopant implantation damage; 75 KeV arsenic implantation followed by 550.degree. C. for 75 minutes and 900.degree. C. for 30 minutes in nitrogen for instance is not sufficient to anneal the implantation damage and results in a leakage current of the order of 1 mA per cm.sup.2. If, however, subsequent to the arsenic implantation, 0.4 KeV hydrogen ions are implanted using a Kaufman ion source with an accelerator current of 200 milliamp, then only 500.degree. to 600.degree. C. for one hour anneal in nitrogen is sufficient to eliminate the arsenic implantation damage. This results in a leakage current of the order of 5 to 25 nA per cm.sup.2 and a complete dopant activation is achieved.
    Type: Grant
    Filed: October 20, 1983
    Date of Patent: June 11, 1985
    Assignee: Westinghouse Electric Corp.
    Inventors: Ajeet Rohatgi, Prosenjit Rai-Choudhury, Joseph R. Gigante, Ranbir Singh, Stephen J. Fonash
  • Patent number: 4372803
    Abstract: An improved method for etch-thinning silicon devices using three sequential tches. The device is pre-thinned in a hot KOH-H.sub.2 O etch. The thinning etch is a hydrofluoric, nitric, acetic acids (1:3:10) and a precise amount of hydrogen peroxide mixture. The cleanup etch is a potassium permanganate, hydrofluoric and acetic acids mixture. The result is a repeatedly specular, smooth, uniform, 10 micron thick membrane over the pixels with a p.sup.+ surface to enhance the CCI optical response.
    Type: Grant
    Filed: September 26, 1980
    Date of Patent: February 8, 1983
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Joseph R. Gigante