Abstract: A method for forming single crystalline silicon-on-insulator (SOI) structures over a silicon substrate includes forming an amorphous silicon layer over an insulating layer and contacting the substrate through the insulating layer. An excimer laser having operating conditions and a wavelength chosen to selectively melt amorphous silicon irradiates the entire substrate surface and is largely non-absorbed by materials other than silicon when incident upon them. Heating of the substrate and other materials is therefore minimal. After a blanket radiation process selectively melts the amorphous silicon layer, cooling conditions are chosen such that a single crystal silicon film is formed during the solidification process due to contact to the single crystal silicon substrate which acts as a seed layer. Various devices may be formed on the SOI islands as well as on exposed portions of the substrate not covered by the SOI islands.

Abstract: A digit signal processor capable of operating at 100 MHZ with a 1.0 volt power supply. The digital signal processor is fabricated by application of strong phase-shift lithography to obtain a 0.12 &mgr;m gate dimension. A dual-mask process is utilized to improve resolution thereby producing high speed, low-voltage processors. A n+/p+ dual-Poly:Si module, and dopant penetration suppression techniques may be utilized.

Abstract: A method for forming single crystalline silicon-on-insulator (SOI) structures over a silicon substrate includes forming an amorphous silicon layer over an insulating layer and contacting the substrate through the insulating layer. An excimer laser having operating conditions and a wavelength chosen to selectively melt amorphous silicon irradiates the entire substrate surface and is largely non-absorbed by materials other than silicon when incident upon them. Heating of the substrate and other materials is therefore minimal. After a blanket radiation process selectively melts the amorphous silicon layer, cooling conditions are chosen such that a single crystal silicon film is formed during the solidification process due to contact to the single crystal silicon substrate which acts as a seed layer. Various devices may be formed on the SOI islands as well as on exposed portions of the substrate not covered by the SOI islands.

Abstract: A method for CMOS device fabrication utilizes selective laser annealing to form raised source/drain contact structures. The raised source/drain contact structures provide for an increased contact area to the source/drain impurity regions. The method includes forming an amorphous silicon layer over the substrate and contacting the substrate surface in the source/drain regions. Dopant impurities are preferably introduced into the amorphous silicon layer. A laser annealing process using an excimer laser, selectively anneals the exposed amorphous silicon and is non-absorptive by other exposed materials so that the other materials are not heated past their respective heating critical points. The laser annealing process preferably urges the diffusion of the dopant impurities from the liquified silicon layer into the substrate in the source/drain regions, thereby forming source/drain impurity regions with shallow junction depths and low sheet resistivity.

Abstract: The present invention provides a method of forming a metal stack structure over a substrate of a semiconductor device, comprising: (a) forming a first metal layer over the substrate, (b) forming a tungsten silicide nitride layer over the first metal layer, (c) forming a second metal layer over the tungsten silicide nitride layer, and (d) annealing the metal stack structure at a diffusion temperature. The tungsten silicide nitride layer inhibits diffusion of the metal in the metal stack. In one embodiment, the annealing is performed in the presence of a forming gas mixture comprising deuterium. In one particularly advantageous embodiment, the metal stack is formed in a contact opening or via. In yet other embodiments, the first metal layer may be a stack layer of titanium and titanium nitride and the second metal layer may be aluminum or copper.

Abstract: The present invention provides a semiconductor device having a metal oxide metal (MOM) capacitor formed over a semiconductor wafer. In one embodiment, the device is a MOM capacitor that includes a first metal layer formed over the semiconductor wafer, a metal silicide layer, such as a tungsten silicide, silicide nitride or a refractory metal silicide, located on the first metal layer and an oxide layer located on the metal silicide layer. The metal silicide layer, which in an advantageous embodiment may be tungsten silicide nitride, resists the corrosive effects of deglazing that may be conducted on other portions of the wafer and is substantially unaffected by the deglazing process, unlike titanium nitride (TiN). Additionally, the metal silicide can act as an etch stop for the etching process. The MOM capacitor is completed by a second metal layer that is located on the oxide layer.

Abstract: The present invention provides a method of forming a metal oxide metal (MOM) capacitor over a semiconductor wafer. The method may include forming a first metal layer over the semiconductor wafer, forming a metal silicide layer, such as a tungsten silicide, silicide nitride or a refractory metal silicide, over the first metal layer and forming an oxide layer over the metal silicide layer. The metal silicide layer, which in an advantageous embodiment may be tungsten silicide nitride, resists the corrosive effects of deglazing that may be conducted on other portions of the wafer and is substantially unaffected by the deglazing process, unlike titanium nitride (TiN). The semiconductor device is completed by forming a second metal layer over the oxide layer.

Abstract: The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes.

Abstract: The present invention provides, for use in an integrated circuit structure having a prior level that includes a foundation dielectric formed over a conductive polycrystalline material, a capacitor comprising first and second electrodes having a capacitor dielectric formed therebetween. The first electrode is formed immediately over the prior level and extends beyond a common area of the first and second electrodes and connects the capacitor to the prior level outside of the common area. The capacitor is free of a direct electrical contact with the prior level; that is, the capacitor is not connected to the prior level by a window or other interconnect structure that extends directly from the capacitor itself within the common area. Electrical connection of the capacitor to the prior level is made outside the common area of the capacitor.

Abstract: A method for making a metal-to-metal capacitor for an integrated circuit includes forming a layer of titanium/titanium nitride on a polysilicon which has been patterned with interlevel dielectrics. A capacitor dielectric is then deposited, followed by patterning with photoresist to delineate the capacitor, etching to remove extraneous dielectric, deposition of aluminum, further patterning and etching to define the capacitor and access area, and removal of photoresist.

Abstract: A high quality dielectric layer, typically silicon dioxide, is formed on a multi-layer deposited semiconductor structure, typically polysilicon or amorphous silicon. The multi-layer structure is formed by varying the silicon deposition rate so as to obtain a low stress deposited silicon structure. The low stress allows for a higher quality dielectric to be formed on the exposed top surface. One application is for thin film transistor gate oxides. Other applications included capacitor dielectrics and the tunnel oxide on the floating gate of EEPROMs.