Patents by Inventor Joseph R. Walston

Joseph R. Walston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DIVIDING A CHIP DESIGN FLOW INTO SUB-STEPS USING MACHINE LEARNING
    Publication number: 20230004698
    Abstract: A method includes generating a plurality of intermediate designs for a chip by executing a first sub-step based on a first plurality of inputs, adding at least one intermediate design of the plurality of intermediate designs to a second plurality of inputs, generating a plurality of final designs by executing a second sub-step of the step of the design flow based on the second plurality of inputs, and selecting using a machine learning model a final design from the plurality of final designs. The first sub-step is a sub-step of a step of a design flow and the first plurality of inputs corresponds to input parameters associated with the first sub-step.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 5, 2023
    Applicant: Synopsys, Inc.
    Inventors: Amzie Allen ADAMS, Joseph R. WALSTON, Piyush VERMA
  • FAIL-SAFE SOFTWARE ACCESS LICENSING CONTROL ON A PER PROJECT BASIS WITHOUT A PRIORI KNOWLEDGE OF PROJECT DETAILS
    Publication number: 20220391477
    Abstract: A request may be received to use a software on a first project. A first set of values may be extracted for a set of features of the first project. A classifier may be used to classify the first project based on the first set of values. It may be determined whether to grant the request to use the software on the first project based on an output of the classifier.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 8, 2022
    Applicant: Synopsys, Inc.
    Inventors: Mathew V. Philip, Joseph R. Walston, Stylianos Diamantidis
  • Context-dependent useful skew estimation for optimization, placement, and clock tree synthesis
    Patent number: 10423743
    Abstract: A method for optimizing a circuit design includes computing clock latency estimates for a set of sequential circuit elements, modifying the clock latency estimates based on relative optimizability of (1) a set of input data paths that are electrically coupled to one or more inputs of the sequential circuit element and (2) a set of output data paths that are electrically coupled to one or more outputs of the sequential circuit element, and optimizing the circuit design based on the modified clock latencies.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 24, 2019
    Assignee: Synopsys, Inc.
    Inventor: Joseph R. Walston
  • CONTEXT-DEPENDENT USEFUL SKEW ESTIMATION FOR OPTIMIZATION, PLACEMENT, AND CLOCK TREE SYNTHESIS
    Publication number: 20180137217
    Abstract: A method for optimizing a circuit design includes computing clock latency estimates for a set of sequential circuit elements, modifying the clock latency estimates based on relative optimizability of (1) a set of input data paths that are electrically coupled to one or more inputs of the sequential circuit element and (2) a set of output data paths that are electrically coupled to one or more outputs of the sequential circuit element, and optimizing the circuit design based on the modified clock latencies.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 17, 2018
    Applicant: Synopsys, Inc.
    Inventor: Joseph R. Walston