Abstract: A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers connected to the semiconductor chip, and a planar spiral differential inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral differential inductor defines an inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees; a sensing membrane operable to become electrically charged when interacting with an ionized fluid, wherein the sensing membrane is operable to electrically communicate with the planar spiral differential inductor; and a fluid property measurement circuit operable to measure a quality factor or inductance of the planar spiral differential inductor and output a fluid property signal.

Abstract: A device has a CMOS metal stack of metal layers oriented substantially horizontally, and an inductor coil oriented substantially vertically in the CMOS metal stack and comprising at least two metal layers of the CMOS metal stack. A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers, wherein the metal stack is connected to the semiconductor chip, a planar spiral inductor comprising at least two metal layers of the metal stack, and a magnetic core in the planar spiral inductor, wherein the magnetic core has magnetic material, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines an inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees.

Abstract: A device has a CMOS metal stack of metal layers oriented substantially horizontally, and an inductor coil oriented substantially vertically in the CMOS metal stack and comprising at least two metal layers of the CMOS metal stack. A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers, a planar spiral inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines an inductor plane having a inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees.

Abstract: A device has a CMOS metal stack of metal layers oriented substantially horizontally in the CMOS metal stack, and a differential inductor coil oriented substantially vertically in the CMOS metal stack and comprising at least two metal layers of the CMOS metal stack. A device having a semiconductor chip having a substrate and an integrated circuit, a metal stack of a plurality of metal layers, wherein the metal stack is connected to the semiconductor chip, and a planar spiral differential inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral differential inductor defines a differential inductor plane having a differential inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the differential inductor plane normal vector is between 1 and 90 degrees.

Abstract: A device has a semiconductor chip with a substrate and an integrated circuit, a metal stack connected to the semiconductor chip, a planar spiral inductor having a magnetic core and comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines an inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees; a sensing membrane operable to attract ions when interacting with an ionized fluid, wherein the sensing membrane is operable to electrically communicate with the planar spiral inductor; and a fluid property measurement circuit operable to measure a quality factor or inductance of the planar spiral inductor or a charge on the magnetic core and output a fluid property signal.

Abstract: A device has a semiconductor chip comprising a substrate and an integrated circuit, a metal stack of metal layers connected to the semiconductor chip, and a planar spiral inductor comprising at least two metal layers of the metal stack, wherein the semiconductor chip defines a semiconductor plane having a semiconductor plane normal vector and the planar spiral inductor defines a inductor plane having an inductor plane normal vector, wherein an angle between the semiconductor plane normal vector and the inductor plane normal vector is between 1 and 90 degrees, a sensing membrane when interacting with an ionized fluid is operable to attract ions, wherein the sensing membrane is operable to electrically communicate with the planar spiral inductor; and a fluid property measurement circuit operable to measure a quality factor or inductance of the planar spiral inductor and output a fluid property signal.

Abstract: An apparatus, system, and method for the manufacturing of an inductor using deep trench isolation (DTI) is disclosed. The apparatus may include a doped substrate forming a well. The apparatus may also include a trench etched in the substrate. The trench may have a shape of a coil. The apparatus may additionally include a dielectric in the trench. The apparatus may further include a conductor within the dielectric in the trench. The dielectric and the conductor may create a first inductor.

Abstract: Aspects provide a device comprising: a substrate doped to form a first well; a first deep trench etched in the substrate; a dielectric in the first deep trench; a first conductor within the dielectric in the first deep trench and biased to create a first depletion region in the substrate proximate the first deep trench, wherein the substrate forms a bottom electrode of a first deep trench isolation varactor and the conductor in the first deep trench forms a top electrode of the first deep trench isolation varactor; a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically charge the first deep trench isolation varactor; and a fluid property measurement circuit operable to determine a change in the capacitance of the first deep trench isolation varactor and output a fluid property signal.

Abstract: Aspects provide fluid ion sensing via inductors using deep trench isolation, comprising: a coil-shaped deep trench etched in a substrate, a dielectric in the deep trench, a conductor within the dielectric in the deep trench, wherein the conductor forms a deep trench inductor, a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically communicate with the deep trench inductor, and a fluid property measurement circuit operable to measure a quality factor or inductance of the deep trench inductor and output a fluid property signal.

Abstract: Inductors and biased deep trench isolation (DTI) varactors may detect the type and concentration of ions in a fluid. An ion sensing device comprises: a deep trench isolation varactor in a substrate having a dielectric and a conductor and biased to create a depletion region in the substrate proximate the deep trench; a sense electrode operable to become electrically charged when interacting with an ionized fluid, wherein the sense electrode is operable to electrically charge the deep trench isolation varactor; an inductor proximate the deep trench isolation varactor and configured so that a change of a characteristic of the deep trench isolation varactor induces a change in the quality factor of the inductor; and a fluid property measurement circuit operable to determine a change in the quality factor of the inductor and output a fluid property signal.

Abstract: An apparatus, system, and method for the manufacturing of an inductor having a high quality factor using deep trench isolation (DTI) is disclosed. The apparatus may include a substrate doped to form a well. The apparatus may also include an inductor coil above a surface of the substrate. The apparatus may further include a trench etched in the substrate, a dielectric in the trench, and a conductor within the dielectric in the trench. The conductor may be biased to create a depletion region below the inductor coil.

Abstract: An apparatus, system, and method for the manufacturing of a varactor using deep trench isolation (DTI) is disclosed. The apparatus may include a substrate doped to form a well. The apparatus may also include a first trench etched in the substrate. The apparatus may additionally include a second trench etched in the substrate parallel to the first trench. The apparatus may further include a dielectric in the first trench and the second trench and a conductor within the dielectric in the first trench and the second trench. The substrate may form a bottom electrode of a first varactor and a second varactor. The conductor in the first trench may form a top electrode of the first varactor. The conductor in the second trench may form a top electrode of the second varactor.

Abstract: Systems and methods for determining an operational limit for a transistor are disclosed. The method may include receiving a set of input parameters related to a transistor and performing an analysis of the transistor based on the set of input parameters. The analysis may include performing a simulation of the transistor under time dependent dielectric breakdown conditions by simulating an operation of the transistor and performing a series of lifetime simulations of the transistor. The series of lifetime simulations may include a simulation of an operation of the transistor based on conditions specified by the input parameters and a different value of at least one operational parameter of the transistor. The analysis may further include comparing respective results of the series of lifetime simulations with a target lifetime of the transistor. The method may include determining an operational limit for the transistor based on a result of the analysis.

Abstract: Systems and methods for determining an operational limit for a transistor are disclosed. The method may include receiving a set of input parameters related to a transistor and performing an age-dependent analysis based on the input parameters. The age-dependent analysis may include performing a non-aging simulation of the transistor by simulating a non-aging operation of the transistor and performing a plurality of aging simulations of the transistor based on aging conditions specified by the input parameters, a different value of at least one operational parameter of the transistor, and an aging recovery effect of the transistor as a function of a usage parameter of the transistor. The analysis may further include comparing respective results of the aging simulations with a result of the non-aging simulation. The method may include determining an operational limit for the transistor based at least on a result of the age-dependent analysis of the transistor.

Abstract: Systems and methods for determining an operational limit for a circuit component are disclosed. The system may include an operational limit generation system including instructions stored in non-transitory computer-readable medium and executable by a processor to receive input parameters related to a component, perform an age-dependent analysis of the component based on the input parameters, and determine an operational limit for the component based on a result of the age-dependent analysis of the component. The age-dependent analysis may include performing a non-aging simulation of the component and a plurality of aging simulations of the component including a simulation of an aging operation of the component based on aging conditions specified by the input parameters, a different value of at least one operational parameter of the component, and effects of self-heating on aging conditions of the component, and comparing results of the aging simulations with a result of the non-aging simulation.

Abstract: A system for reliability testing may include one or more sockets to receive respective semiconductor devices. A switch driver and a network of switches may control a voltage or current applied to each of the respective semiconductor devices. A measurement system may read signals from the respective semiconductor devices during testing and may calculate parametric values while reliability testing is ongoing.

Abstract: A non-transitory computer-readable medium comprising instructions executable by a processor to receive a set of input parameters related to a circuit component and perform an age-dependent analysis of the circuit component based on the set of input parameters. The age-dependent analysis of the circuit component includes performing a series of automated simulations of a non-aged model of the circuit component using each of multiple values of a first operational parameter, performing a series of automated simulations of an aged model of the circuit component using each of the multiple values of the first operational parameter, and comparing respective results of the automated simulations of the non-aged and aged models of the circuit component. The instructions are further executable to determine an operational limit for the circuit component based at least on the age-dependent analysis of the circuit component.

Abstract: A burn-in board for burn-in testing of semiconductor devices includes a strip socket mounted to a PCB. The strip socket includes a socket base configured to receive a device strip including an array of semiconductor devices, and a socket lid including at least one heating block. The socket lid is movable moved between (a) an open position allowing the device strip to be mounted on the socket base and (b) a closed position in which the socket lid including the heating block(s) is closed down on the mounted device strip. The strip socket includes conductive contacts configured to contact individual semiconductor devices on the device strip to allow selective monitoring of individual semiconductor devices during a burn-in test process. The burn-in board may also include heating control circuitry to control the heating block(s) during the burn-in test process.

Abstract: A burn-in board for burn-in testing of semiconductor devices includes a strip socket mounted to a PCB. The strip socket includes a socket base configured to receive a device strip including an array of semiconductor devices, and a socket lid including at least one heating block. The socket lid is movable moved between (a) an open position allowing the device strip to be mounted on the socket base and (b) a closed position in which the socket lid including the heating block(s) is closed down on the mounted device strip. The strip socket includes conductive contacts configured to contact individual semiconductor devices on the device strip to allow selective monitoring of individual semiconductor devices during a burn-in test process. The burn-in board may also include heating control circuitry to control the heating block(s) during the burn-in test process.