Abstract: A semiconductor device includes at least one component which is vulnerable to damage during scan testing for a particular input data configuration, and supports a safe mode in which this particular input data configuration is disabled. The semiconductor device also includes a port for receiving an input scan vector for scan testing, and an authorization unit connected to said port. The authorization unit maintains the device in safe mode if an input scan vector does not satisfy at least one predetermined criterion. In one particular implementation, the authorization unit generates a digital signature for the input scan vector, which is then compared to a signature portion included within the input scan vector itself. Scan testing is enabled providing that this comparison finds a match.

Abstract: A semiconductor device includes at least one component which is vulnerable to damage during scan testing for a particular input data configuration, and supports a safe mode in which this particular input data configuration is disabled. The semiconductor device also includes a port for receiving an input scan vector for scan testing, and an authorisation unit connected to said port. The authorisation unit maintains the device in safe mode if an input scan vector does not satisfy at least one predetermined criterion. In one particular implementation, the authorisation unit generates a digital signature for the input scan vector, which is then compared to a signature portion included within the input scan vector itself. Scan testing is enabled providing that this comparison finds a match.

Abstract: A semiconductor device can be subjected to scan testing by using an input scan test vector. This input scan test vector is processed by the device to produce an output scan test vector, which can be used for diagnostic purposes with respect to the device. There are certain locations in this output scan test vector that may be indeterminate in value, even for a correctly functioning device. In other words, it is not possible to predict beforehand what values the output scan test vector will have at these locations. Therefore, an output mask vector is provided that identifies those locations in the output scan test vector that are indeterminate. This mask vector is then combined with the output scan test vector using a logical operation to produce a determinate masked output scan test vector. For example, if all the indeterminate locations are flagged by a 1 in the mask vector, then using OR for the logical operation will ensure that the output for these locations is always a 1.