Patents by Inventor Joseph Regh

Joseph Regh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7759566
    Abstract: Optimized tone wood for acoustical performance and methods for optimizing tone wood are described. The longitudinal to cross-grain stiffness ratio, the acoustical mass, and damping of tone wood are adjusted to improve volume and quality of tonal output. These properties are adjusted by selectively removing a portion of summer growth of the wood to reduce cross-grain stiffness while retaining the winter growth of the wood for longitudinal stiffness. Damping materials can modify the effects of the summer growth removal.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: July 20, 2010
    Inventor: Joseph Regh
  • Publication number: 20090107318
    Abstract: Optimized tone wood for acoustical performance and methods for optimizing tone wood are described. The longitudinal to cross-grain stiffness ratio, the acoustical mass, and damping of tone wood are adjusted to improve volume and quality of tonal output. These properties are adjusted by selectively removing a portion of summer growth of the wood to reduce cross-grain stiffness while retaining the winter growth of the wood for longitudinal stiffness. Damping materials can modify the effects of the summer growth removal.
    Type: Application
    Filed: October 26, 2007
    Publication date: April 30, 2009
    Inventor: Joseph Regh
  • Patent number: 4060427
    Abstract: A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivity-determining impurity of the same type through the same aperture into said substrate.The method has particular application when the electrically insulative layer is a composite of two layers, e.g., a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to provide an undercut beneath the silicon nitride ion implantation barrier layer.
    Type: Grant
    Filed: April 5, 1976
    Date of Patent: November 29, 1977
    Assignee: IBM Corporation
    Inventors: Conrad A. Barile, Robert M. Brill, John L. Forneris, Joseph Regh
  • Patent number: 3982974
    Abstract: A method of making an integrated circuit wherein a subcollector diffusion mask is formed on a semiconductor wafer. A principal impurity of a predetermined conductivity type is then diffused through windows in the mask and into the wafer to form subcollector regions spaced from each other. A compensating impurity of a conductivity type opposite that of the principal impurity is then diffused through the same mask windows into the subcollector regions to a relatively shallow depth. An epitaxial layer is then grown on the wafer during which an amount of the principal impurity diffuses from the subcollector regions into the gas and then into the epitaxial layer and the wafer in areas thereof exterior to the peripheries of the subcollector regions thereby resulting in an autodoping effect. However, the compensating impurity simultaneously diffuses into the exterior areas so as to compensate approximately for the principal impurity and thereby to counteract the autodoping effect of the principal impurity.
    Type: Grant
    Filed: December 24, 1974
    Date of Patent: September 28, 1976
    Assignee: International Business Machines Corporation
    Inventors: William A. Edel, Joseph Regh