Abstract: The present invention relates to a method for reducing blood pressure by stimulating lymphatic vessel growth and/or lymphangiogenesis in the kidneys.

Abstract: Certain aspects of the present disclosure provide a voltage transient detection circuit. The circuit generally includes a first switch having a first terminal coupled to an input signal source node, and a second switch having a first terminal coupled to the input signal source node. The apparatus includes a first shunt capacitive element coupled to a second terminal of the first switch, a second shunt capacitive element coupled to a second terminal of the second switch, a differential circuit having a first input coupled to the second terminal of the first switch, a second input coupled to the second terminal of the second switch, and an output coupled to an output node of the voltage transient detection circuit. For certain aspects, the apparatus also includes a first current source (selectively) coupled to the first shunt capacitive element and a second current source (selectively) coupled to the second shunt capacitive element.

Abstract: A method of automating organization of a defined space is provided. Spatial data about the defined space and location data of objects in the defined space are received from a number of input devices. A baseline organization scheme of objects in the defined space is created. User profile data is received for an organizer, and a recommended organization scheme of items in the defined space is created based on comparison of the baseline organization scheme with the user profile data for the organizer. A presentation of the recommended organization scheme is generated by a number of user interfaces. Locations of items in the defined space relative to the recommended reorganization scheme are monitored utilizing a number of sensors, and an alert is sent to the organizer if locations of items in the defined space deviate from the recommended organization scheme beyond a predefined threshold.

Abstract: Certain aspects of the present disclosure provide a voltage transient detection circuit. The circuit generally includes a first switch having a first terminal coupled to an input signal source node, and a second switch having a first terminal coupled to the input signal source node. The apparatus includes a first shunt capacitive element coupled to a second terminal of the first switch, a second shunt capacitive element coupled to a second terminal of the second switch, a differential circuit having a first input coupled to the second terminal of the first switch, a second input coupled to the second terminal of the second switch, and an output coupled to an output node of the voltage transient detection circuit. For certain aspects, the apparatus also includes a first current source (selectively) coupled to the first shunt capacitive element and a second current source (selectively) coupled to the second shunt capacitive element.

Abstract: Method and apparatus is disclosed for providing a controlled pre-charging current for capacitive loads coupled to a boost converter. For at least some embodiments, the boost converter may include a high-side field effect transistor (FET) and a low-side FET. The boost converter may provide the pre-charge current by periodically enabling the high-side FET while the low-side FET is maintained in an off state. The high-side FET may be enabled by a square-wave signal. The pre-charge current may be delivered until the output voltage of the boost converter exceeds a reference voltage. After the output voltage exceeds the reference voltage, the boost converter may transition to a normal (switching) operation.

Abstract: Techniques for improving the transient response in a switching converter are provided. An example of a gate driving circuit for driving a high-side switch in a switching converter according to the disclosure includes a first switch operably coupled to a source lead and a gate lead of the high-side switch, a first super source follower circuit operably coupled to the gate lead of the high-side switch, and a mid-voltage power supply operably coupled to the first super source follower circuit.

Abstract: Method and apparatus is disclosed for providing a controlled pre-charging current for capacitive loads coupled to a boost converter. For at least some embodiments, the boost converter may include a high-side field effect transistor (FET) and a low-side FET. The boost converter may provide the pre-charge current by periodically enabling the high-side FET while the low-side FET is maintained in an off state. The high-side FET may be enabled by a square-wave signal. The pre-charge current may be delivered until the output voltage of the boost converter exceeds a reference voltage. After the output voltage exceeds the reference voltage, the boost converter may transition to a normal (switching) operation.

Abstract: An apparatus and method for to incrementally reduce (e.g., de-rate) a power supply voltage output (VOUT) of a regulator to multiple subsystems in response to detecting high power conditions in a client device is described. In one instance, multiple low power client devices and a high power consumption client device are coupled to a power grid of the power management system with a power management integrated circuit (PMIC) supplying power to the power grid. The PMIC includes a buck-or-boost switching regulator including a load current adjustment device to de-rate the high power consumption device when a sum of the current consumed by the high power consumption device and the low power client devices is above a predetermined threshold.

Abstract: Techniques for improving the transient response in a switching converter are provided. An example of a gate driving circuit for driving a high-side switch in a switching converter according to the disclosure includes a first switch operably coupled to a source lead and a gate lead of the high-side switch, a first super source follower circuit operably coupled to the gate lead of the high-side switch, and a mid-voltage power supply operably coupled to the first super source follower circuit.

Abstract: A loop compensation circuit includes a differential difference amplifier having a first transconductance stage with a first input terminal and a second input terminal. The first input terminal is coupled to a voltage reference and the second input terminal is coupled to a feedback node. The amplifier also includes a second transconductance stage having a third input terminal and a fourth input terminal. The third input terminal is coupled to a virtually specified fixed voltage and the fourth input terminal is coupled to a fixed specified voltage. The loop compensation circuit also includes a feedback impedance coupled between an output of the differential difference amplifier and the third input terminal and a second impedance between the third input terminal and the fixed specified voltage.

Abstract: A loop compensation circuit includes a differential difference amplifier having a first transconductance stage with a first input terminal and a second input terminal. The first input terminal is coupled to a voltage reference and the second input terminal is coupled to a feedback node. The amplifier also includes a second transconductance stage having a third input terminal and a fourth input terminal. The third input terminal is coupled to a virtually specified fixed voltage and the fourth input terminal is coupled to a fixed specified voltage. The loop compensation circuit also includes a feedback impedance coupled between an output of the differential difference amplifier and the third input terminal and a second impedance between the third input terminal and the fixed specified voltage.

Abstract: Methods, computer program products, and systems are presented. The methods include, for instance: receiving a request for a response to have a piece of annotative data on a literary text from a user; ascertaining metadata to generate the response is available for the literary device system; identifying a process of the literary device system that is associated with the request; running the process with the request and generating the response based on the metadata; and producing the response to the user such that the user is presented with the annotative data on the literary text.

Abstract: The present disclosure pertains to circuits and methods for controlling a boost switching regulator based on inductor current. An input voltage is coupled to a first terminal of an inductor and the second terminal of the inductor is alternately coupled between a reference voltage and a boosted output voltage. The input voltage is further coupled to a first terminal of an integrator circuit, and a second terminal of the integrator circuit may be alternately coupled between the reference voltage and the boosted output voltage, for example, to produce a voltage corresponding to a current in the inductor. The present circuit may be used for voltage control or current control modes, or both, in a boost switching regulator.

Abstract: An apparatus improves efficiency of a non-inverting buck-or-boost regulator by reducing an amount of switching of the buck-or-boost regulator. A high side buck transistor and a high side boost transistor of the buck-or-boost regulator are turned on. A low side buck transistor and a low side boost transistor are turned off. The turning on and turning off short an input voltage node to an output voltage node of the buck-or-boost regulator to prevent switching of the high side buck transistor and the high side boost transistor. The turning on and turning off are based on a voltage difference between the input voltage node and the output voltage node.

Abstract: An apparatus and method for to incrementally reduce (e.g., de-rate) a power supply voltage output (VOUT) of a regulator to multiple subsystems in response to detecting high power conditions in a client device is described. In one instance, multiple low power client devices and a high power consumption client device are coupled to a power grid of the power management system with a power management integrated circuit (PMIC) supplying power to the power grid. The PMIC includes a buck-or-boost switching regulator including a load current adjustment device to de-rate the high power consumption device when a sum of the current consumed by the high power consumption device and the low power client devices is above a predetermined threshold.

Abstract: In one embodiment, a switching regulator includes an inductor, a first switch, and a second switch. The first and second switches generate current in the inductor. Inductor current may flow through the second switch with both a positive and negative polarity. Voltages on terminals of the second switch may be sensed, and an offset applied to generate a level shifted signal. In one embodiment, the switching regulator is a boost switching regulator, and the offset is generated using a current source. Matched MOS transistor switches may be used to couple voltages on terminals of the second switch to amplifier inputs, and the offset is introduced across an MOS switch coupled between one amplifier input and the output.

Abstract: In one embodiment, a switching regulator includes an inductor, a first switch, and a second switch. The first and second switches generate current in the inductor. Inductor current may flow through the second switch with both a positive and negative polarity. Voltages on terminals of the second switch may be sensed, and an offset applied to generate a level shifted signal. In one embodiment, the switching regulator is a boost switching regulator, and the offset is generated using a current source. Matched MOS transistor switches may be used to couple voltages on terminals of the second switch to amplifier inputs, and the offset is introduced across an MOS switch coupled between one amplifier input and the output.

Abstract: The present disclosure pertains to circuits and methods for controlling a boost switching regulator based on inductor current. An input voltage is coupled to a first terminal of an inductor and the second terminal of the inductor is alternately coupled between a reference voltage and a boosted output voltage. The input voltage is further coupled to a first terminal of an integrator circuit, and a second terminal of the integrator circuit may be alternately coupled between the reference voltage and the boosted output voltage, for example, to produce a voltage corresponding to a current in the inductor. The present circuit may be used for voltage control or current control modes, or both, in a boost switching regulator.

Abstract: Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

Abstract: Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.