Abstract: A capacitor including a first active layer capacitively coupled to a second active layer, the second active layer being capacitively coupled to a third layer, the third layer being capacitively coupled to a fourth layer, wherein an anode of the capacitor is connected to one of the first and second active layers, and a cathode of the capacitor is connected to the other one of the first and second active layers, and wherein the third layer is left floating. The fourth layer may be connected to a supply voltage, such as but not limited to, ground.

Abstract: Circuitry including a BGREF (bandgap voltage reference) comparator including a plurality of MOS transistors that compare a resistor divided supply voltage to a function of at least two process parameter voltages.

Abstract: A charge pump stage comprising a pulse train which injects energy into a gate of a charge transfer transistor of the charge pump stage, wherein a modified output of the pulse train is input to a bulk of the charge transfer transistor such that a bulk voltage of the charge transfer transistor is raised to a level not greater than the minimum of a source voltage and a drain voltage of that charge transfer transistor. A method for operating the charge pump stage is also disclosed.

Abstract: Circuitry including a voltage regulator including a first stage and a second stage, wherein an output of the first stage is coupled to an input of the second stage, wherein current of the second stage is mirrored through a current path to a current mirror driver, the current mirror driver adapted to perform a first Class AB action including at least one of sourcing and sinking current from a voltage supply VPP, wherein an output of the current mirror driver is connected to an output of the voltage regulator, and a first circuit connected to the current path and adapted to sample current in the current path, wherein during steady state current in the current path, the first circuit provides negligible current to the output of the voltage regulator, and during transient current conditions, the first circuit performs a second Class AB action complementary to the first Class AB action including at least one of sinking and sourcing current from the voltage supply VPP.

Abstract: A discharge device comprising a transistor configured as a source follower, a capacitance load to be discharged connected via a switch to a source terminal of the source follower, a reference voltage connected to a gate terminal of the source follower, and a current load element connected to a drain terminal of the source follower.

Abstract: An operational amplifier comprising an inverting stage transistor that drives current to an output of the operational amplifier through a current path, and an auxiliary transistor that adds transient current to the current path and which remains dormant under steady-state conditions.

Abstract: A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

Abstract: According to some embodiments of the present invention, a non-volatile memory cell may be operated using a charge pump circuit. The charge pump circuit may be adapted to output a first and second voltage level, and the charge pump circuit may be connected to a first circuit segment, including a select transistor associated with the memory cell, through a switch. When the charge pump circuit is outputting power at the first voltage level, the switch may be conducting and the select transistor line may be charged. When the charge pump circuit is outputting power at the second voltage level, the switch may be opened and a second circuit segment, including a bit line associated with the memory cell, may be charged.

Abstract: A discharge device comprising a transistor configured as a source follower, a capacitance load to be discharged connected via a switch to a source terminal of the source follower, a reference voltage connected to a gate terminal of the source follower, and a current load element connected to a drain terminal of the source follower.

Abstract: A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control terminal connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.

Abstract: An operational amplifier comprising an inverting stage transistor that drives current to an output of the operational amplifier through a current path, and an auxiliary transistor that adds transient current to the current path and which remains dormant under steady-state conditions.

Abstract: A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control tern connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.

Abstract: According to some embodiments of the present invention, a non-volatile memory cell may be operated using a charge pump circuit. The charge pump circuit may be adapted to output a first and second voltage level, and the charge pump circuit may be connected to a first circuit segment, including a select transistor associated with the memory cell, through a switch. When the charge pump circuit is outputting power at the first voltage level, the switch may be conducting and the select transistor line may be charged. When the charge pump circuit is outputting power at the second voltage level, the switch may be opened and a second circuit segment, including a bit line associated with the memory cell, may be charged.

Abstract: A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

Abstract: A charge pump stage comprising a pulse train which injects energy into a gate of a charge transfer transistor of the charge pump stage, wherein a modified output of the pulse train is input to a bulk of the charge transfer transistor such that a bulk voltage of the charge transfer transistor is raised to a level not greater than the minimum of a source voltage and a drain voltage of that charge transfer transistor. A method for operating the charge pump stage is also disclosed.

Abstract: A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

Abstract: A circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (Vct) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control tern connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as Vct.

Abstract: A method for operating a charge pump, the method including biasing a bulk of a charge pump stage so as to reduce body effect without forward biasing diodes of the charge pump stage.

Abstract: A method for selective conductivity etching of a silicon carbide (SiC) semiconductor includes forming a p-type SiC layer on a substrate layer, forming an n-type SiC layer on the p-type SiC layer, and photoelectrochemically etching selected portions of the n-type SiC layer by applying a bias voltage to the n-type SiC layer in a hydrofluoric acid (HF) solution while exposing the layer to a pattern of UV light. The bias potential is selected so that the n-type SiC layer will photo-corrode and the p-type SiC layer will be inert and act as an etch stop. The light pattern exposure of the n-type SiC layer may be done by applying a photolithographic mask to the layer, by projecting a collimated light beam through a patterned mask, or by scanning with a focused micrometer-sized laser beam on the semiconductor surface.

Abstract: A method for fabricating a single crystal silicon on insulator material by forming oxidized layers underneath epi islands without damaging the surface quality of the silicon. In an illustrative embodiment, an epitaxial layer of p-type silicon is grown on a substrate of n-type silicon. A plurality of islands are defined from the epitaxial layer. A semiconductor device is fabricated from one of the p-islands by electrochemically anodizing a region of the substrate beneath that p-island, which p-island can be used to fabricate a selected semiconductor device. If n-type material is required for device fabrication, a device layer of n-type silicon can be grown on the surface of a p-islands and that p-island can be anodized and oxidized to form the insulating layer between the device layer and substrate. In this manner, MOS transistors and other devices may be fabricated for operation at temperatures of up to 500.degree. C.