Abstract: A memory refresh circuit controls the refreshing of dynamic RAM included in a system wherein a control store outputs micro-code instructions to control the system operation in response to sequences specified by a sequence and interrupt logic circuit (SIL). A counter transmits certain counts of system machine cycles to an array logic device. In response to one count, the array logic device generates a memory refresh request signal which is applied to a RAM address logic circuit (RAL). The RAL monitors the micro-code instruction output at each machine cycle to determine whether the instruction will access the dynamic RAM during that machine cycle, and if no memory access is detected, the RAL generates a signal to initiate a memory refresh operation, which operation requires two machine cycles to complete.The array logic device also monitors the micro-code instructions to determine if and when a refresh operation was initiated.